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error in compling verilog module

Altera_Forum
Honored Contributor II
‎07-18-2015 02:27 PM
1,992 Views

I write this module and when compile it get error "Error (12153): Can't elaborate top-level user hierarchy" 

file attached. 

can any one help me?
wrapper.v
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Altera_Forum
Honored Contributor II
‎07-19-2015 09:15 AM
742 Views

Hi, 

 

Just wonder if you have tried to add your file to the Quartus II and then set this file as top level entity? It seems like Quartus II could not identify the top level file during compilation.
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Altera_Forum
Honored Contributor II
‎07-19-2015 09:26 AM
742 Views

Hi  

I set this file as top entity but still give this error. 

 

Thanks!
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Altera_Forum
Honored Contributor II
‎07-22-2015 11:16 AM
742 Views

Hi  

change  

always@(posedge csi_clockreset_clk or csi_clockreset_reset_n) 

to 

always@(posedge csi_clockreset_clk or negedge csi_clockreset_reset_n)  

and correct.
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