i need to run my design module at 160kbps ....so i used the clock divider as below:
module clock_divider( master_clk, clk_div );
input master_clk; // 27MHz
output reg clk_div;
reg [6:0] count;
always @ (posedge master_clk)
begin
if (count > 168) //160kbps
begin
count <= 0;
clk_div <=~clk_div;
end
else
count <= count + 1'b1;
end
endmodule
the problem is how to setting the clock input in the test bench module in order to do the simulation on my design.....can anyone help me??
thanks,
