multiple block data files (.bdf)

[Altera_Forum]

Hi 

 I am a beginner just started with 3c120-kit. I have made a design using the Block Editor. All design has been put into one single Block Design File (.bdf). The design runs ok, but the single bdf is not very good from point of view of the structure. I can easily split this file into 10 submodules. But when saving the partial designs in separate bdf's, the compiler wont understand the connection between the files, something which can easily been understood in normal programming languages (external references). When I am trying to make a topDesign using blocks, Quartus does not link the names in the submodules, so it does not work.  How can one link easily (!!!) some bdf's to make a complete design, without having to make a lot of name mapping, which is done automatically by Quartus when the instances are in one single bdf, but which seems not to work, when splitting into different bdf's?  Hints are much appreciated.

[Altera_Forum]

Are you talking about having them in parrallel or heirarchical. I dont think quartus will support parrallel Bdfs. 

 What you usually have to do is create a bsf (symbol file) from your bdf file (file -> create / update -> create symbol file from current file). Then the sub module should be avilable to place in your top level bdf.

[Altera_Forum]

Splitting top level bdf in multiple 'parallel' files would be convenient for me, too. 

But, as Tricky said, I think this feature is not supported and it will not. If it's only a matter of visualization/printing, you can organize the single bdf this way: - in the page setup dialog define the number pages you want your schematic to span. - in the bdf editor options, enable "Show page breaks" - place your schematics elements into the desired pages, whose borders now appear on

[Altera_Forum]

Hi Tricky and Cris72 

 Thank you for info. The basic problem I have, is that the symbols don't get the reference names from the bdf, so the compiler does not connect the names as it does in a single bdf. I would like to have one top-bdf which references the other bdf's in a hierarchical manner and connecting all names automatically, as is done in a single bdf. But that does not work. Currently I am trying to create verilog code from the subbdfs and then to connect them but I have not yet come to a point of success with that approch. I am coming from Object Oriented programming in Smalltalk. There there are very very powerfull concepts for connecting large amounts of names automatically by the great concept of objects. But this seems not to have taken place in hardware design software.  Hopefully, I will find a way to use the computer for name referencing also for FPGA design.  As stated I am a beginner, I have not done complicated things yet with Quartus...

[Altera_Forum]

with the graphical edititor you have to start from the bottom up. You create a bdf, then go  

 file -> create/update -> symbol file for current file  This will create a .bsf file and add it to your current project that will allow you to place the symbol in another bdf. You can do this for as many levels of heiracrchy as you want (I have old designs that go through about 10 layers of BDF).  Be warned, until you try and synthesise the design it may not fully understand the heirarchy and might not open the other bdf when you click on the symbol in the higher level. But it definatly works because ive done it and we have plenty of designs that do it.

[Altera_Forum]

Ok, Tricky 

 I have done just what you suggest in a trivial design:  1) Input.bdf which contains just a input pin and a busline called 'connectToOutput'. 2) Output.bdf which contains just an output pin and a busline called also 'connectToOutput'. 3) symbol file generated for both bdf 4) testFpga.bdf as top, added the two symbols. compiler will say error, no logic in top design 4a) renamed to testFpgaHierarchy.bdf 5) testFpa.bdf which contains both pins and both buslines 'connectToOutput'. compiler will correctely compile! 5a) copy into testFpgaDirect.bdf 6) Archiving the file in testFpga.qar and attached to this post

[Altera_Forum]

Ahh 

 Well yes - you cannot connect signal names over multiple BDFs BDF files are self contained. This is the same in any HDL language also. Each block has to be self contained.

[Altera_Forum]

Hi Tricky 

 That is just what I feared: hardware experts don't think about software comfort.  I am very disappointed, but I have no choice  regards  Flexi

[Altera_Forum]

Its not to do with software comfort - global signals are bad practice (and frowned on in software afaik). You have to try and think about firmware design in terms of hardware. In hardware it is impossible to have a signal shared by 2 components - all signals have to go in and out via pins on the device.

[Altera_Forum]

Global signals that automagically drill through the hierarchy is not only a poor practice assuming your tools would allow for it (never seen it myself for good reason) but it would open you up for all kinds of nasty bugs where things would get wired up that you were not expecting. If you find you have signals running all over the place in your schematics at various levels perhaps the granularity of your design is causing this. 

 I would also take a look at conduits, you might find them handy when interconnecting various block diagrams in a design.