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question about wait command in VHDL

Altera_Forum
Honored Contributor II
‎06-06-2016 06:09 PM
1,179 Views

Anybody interested in answering a stupid question from a newbee? 

 

Ashenden writes in his book "the Designers guide to VHDL"(second edition page 118) the syntax of the VHDL wait statement is  

 

wait [on signal_name{,...}] 

[until boolean_expression] 

[for time_expression];  

any combination of 3 obtions is allowed. 

 

HOWEVER syntax  

 

quartus2 version 13 NOT accepts  

 

storage: process is 

. 

. 

. 

wait on d0;  

end process storage; 

 

and DOES accept: 

 

storage: process(d0) is 

. 

. 

. 

 

end process storage; 

 

hence not using the wait statement, but the equivalent semantic  

 

extremely stupid facing icon
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Altera_Forum
Honored Contributor II
‎06-06-2016 09:06 PM
465 Views

This is because sensitivity lists are ignored for synthesis, and wait statements are not. A circuit cannot act on a signal'event. The 2nd process will get compiled ignoring the sensitivity list.

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