Hi
I implemented the following ram:
getting_data:process(clk)
begin
if rising_edge(clk) then
if wr_en='1' then
array_data(conv_integer(address_write1))<=data_in;
else
data_out1<=array_data(conv_integer(address_read1));
end if;
end if;
end process;
I write data to the RAM with address_generator in other file (top-level):
address_write1<=address_write1+1...
and read data with
address_read1<=address_read1+1
In modelsim it works perfect but after timing simulation
I never managed to read data in right way... (*vho,*.sdo)
need help to read data (I think it should not be difficult)... :confused:
thanks
ari
