signaltap compile error

[Altera_Forum]

The device is Cyclone IV E EP4CE115F29C8, before adding signaltap module, the whole project works fine from compile to generate sof file. but after I add the signaltap module, there are errors: 

 Error (12077): Node instance "\stp_non_zero_ram_gen:stp_buffer_ram" instantiated with unknown parameter "ecc_pipeline_stage_enabled" Error (12077): Node instance "\stp_non_zero_ram_gen:stp_buffer_ram" instantiated with unknown parameter "stratixiv_m144k_allow_dual_clocks" Error (12077): Node instance "\stp_non_zero_ram_gen:stp_buffer_ram" instantiated with unknown parameter "width_eccstatus" Error (12154): Can't elaborate inferred hierarchy "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram" Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 4 errors, 480 warnings  Error: Peak virtual memory: 976 megabytes  Error: Processing ended: Mon Aug 24 13:43:39 2015  Error: Elapsed time: 00:01:48  Error: Total CPU time (on all processors): 00:02:00  Have no idea why this happen and how to fix it

[Altera_Forum]

Which Quartus II version are you using? Have you tried with different versions to see if still occur?

[Altera_Forum]

I am running into something similar. How did you fix this?