Hi, I hope I'm not asking something that already been asked before but here goes:
I've tried simulating the altdq_dqs2 megafunction (tageting arria V device) but I'm getting modelsim mixed language errors as I'm simulating the megafunction using a VHDL testbench and it would seem that while the megafunction generates the core with a VHDL wrapper, the core is still written in verilog (hence the mixed language errors)...
I'm using the free altera-modelsim for simulation and quartus 13.0sp1 web edition.
Is it infact possible to simulate a megafunction such as this using the single language version of modelsim-altera, and a vhdl testbench or am I expected to purchase modelsim/DE/PE?
It would seem that starting with the V series FPGA's (cycloneV, ArriaV,stratixV) a number of megafunctions (transceivers for example) can't be simulated with a VHDL testbench.
I even tried compiling the design and generating a .vho netlist and simulating it, but quartus 13.0sp1 doesn't generate .vho netlists for these device!
Many thanks in advance.
MM
