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vhdl for loop and synthesis

Altera_Forum
Honored Contributor II
‎09-21-2016 10:01 AM
1,084 Views

Hi, 

I'm usingfor i in 0 to idx-1 generate 

idx could be 0. Is this a problem for Quartus? 

Thanks.
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Altera_Forum
Honored Contributor II
‎09-21-2016 10:32 AM
376 Views

No - it is a null range and will be understood. The loop wont get entered.

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