I'm attempting to hit 150 MHz in a dual processor design I have, and I'm almost there. Fmax is around 145 right now. One of the suggestions in the Timing Optimization Advisor is to use the global clock for low-skew and speed-critical signals.
When I click "List all clocks", it shows me the two outputs from my PLL, TCKUTAP and UPDATEUSER from altera_internal_jtag, and PLD_CLOCKINPUT[1] which is hooked to the input of my PLL. These are all using the global clock except for PLD_CLOCKINPUT[1]. I'm having trouble finding documentation on how I would change that to use the global clock, or if it even should.
Also what are TCKUTAP and UPDATEUSER, and should they be constrained? Because they're the only clock signals that aren't right now.
