Cyclone Ii To Adc Interface Problems

[Altera_Forum]

ADC Interface Problems

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I am using a Cyclone II Fpga.

I am trying to interface between a Nios Processor and a two serial output Linear ADCs LTC 1867(16 bit) for data acq and display of peak detect values.

I thought about using a SPI SOPC Builder Master, and the two ADCs as slaves, but I have been told that this is to slow for our application, and we need to include a reference Clock and we also need to able to alter the sample rate of the ADCs to suit our process.

The two ADCs are configured differentially so each ADC will have 4 input channels (8 sample inputs) coming from sensors.

We want to use serial output ADC types.

I have been thinking about a method were the ADC,s feed into a SIPO register in (VERILOG) to convert to a SPI to parallel output. Then feed a demux which would contain 4 registers holding four ADC conversions.

Instead of putting them into a FIFO we would place them into a memory

and build of each of samples in parallel in the memory 

until we had the required amount stored, as apposed to 

the FIFO storage method.

A peak Detect operation would be carried out on the stored data in memory.

A software routine would take a copy of the stored data for displaying

Of peak acquisition and upper and lower values of the positive half sine wave.

I have some Questions, can you help

1.) Could this design process be easily implemented in verilog and using

SOPC Builder and mega functions, could you give me explanations,

Is there a simpler method?

2.) I can produce a sipo in SOPC Builder but I not sure about the demux

and storing into memory stage it to be carried out.

3.) I know how a peak search is done in software , but if the data register in memory is to remainthe same and not altered how would you create a peak detect in hardware to indicate to software the peak position.

I am new to Verilog

Thanks

Tom Murray

[Altera_Forum]

You didn't tell a word about intended ADC throughput. Generally I would prefer a generic HDL (Verilog or VHDL) design for the data acquisition and preprocessing task, at least for medium or higher speed. It can deliver the data to the SOPC design part, e.g. through a FIFO or a dual port memory.