Issues with Quartis...

Altera_Forum · ‎11-09-2005

See attachment

Altera_Forum · ‎11-09-2005

I am having another issue now as well as those last two. Quartis doesnt seem to want to compile the VHDL code now after some slight changes. It doesnt give me any errors, it just doesnt do anything. This same code compiles and runs fine in modelsim.

Thanks for any help!

Altera_Forum · ‎11-10-2005

Regarding the counting in your statemachine:

How are the signals in the if statement related to the statemachine clock?

Your described behaviour may suggest that at least RxReady is asynchronous

to clk16xt.

As for the memory:

I'm not sure how well it should transform automatically into a memory block,

but you constructed a global clear in the reset state.

Something the embedded memory blocks are incapable of.

Cheers, Roger

Altera_Forum · ‎11-10-2005

vitzh,

Your VHDL coding style sucks, sorry man! Compiling VHDL for simulation is much different than synthesis.

Look at your code, can you draw a circuit from it? If no, then neither can your synthesis tool, or if it can, you probably wont get what you were hoping for.

VHDL is not C/C++, it doesn't execute line1, line2, etc... I looked over you code very briefly it's messy and doesn't make much sense, sorry man but that is probably what your synthesis tool is trying to tell you.

Start with some simple stuff, create a state machine to toggle a bit or something.

Real quick, 2 state machine implementations, both have 9 states, but will be synthesized differently.

--

-- This will give you a binary state machine with 9 states when synthesized.

--

subtype Sreg0_type is STD_LOGIC_VECTOR (0 to 3);

constant S1: Sreg0_type := "0000";

constant S2: Sreg0_type := "0001";

constant S3: Sreg0_type := "0010";

constant S4: Sreg0_type := "0011";

constant S5: Sreg0_type := "0100";

constant S6: Sreg0_type := "0101";

constant S7: Sreg0_type := "0110";

constant S8: Sreg0_type := "0111";

constant S9: Sreg0_type := "1000";

signal Sreg0: Sreg0_type;

-----------------------------------------------------------------------------------

--

-- This will give you a one-hot state machine when synthesized.

--

subtype Sreg0_type is STD_LOGIC_VECTOR (0 to 8);

constant S1: Sreg0_type := "000000001";

constant S2: Sreg0_type := "000000010";

constant S3: Sreg0_type := "000000100";

constant S4: Sreg0_type := "000001000";

constant S5: Sreg0_type := "000010000";

constant S6: Sreg0_type := "000100000";

constant S7: Sreg0_type := "001000000";

constant S8: Sreg0_type := "010000000";

constant S9: Sreg0_type := "100000000";

signal Sreg0: Sreg0_type;

Doug

Altera_Forum · ‎11-11-2005

--- Quote Start ---

originally posted by rsteiner@Nov 10 2005, 05:59 AM

as for the memory:

i'm not sure how well it should transform automatically into a memory block,

but you constructed a global clear in the reset state.

something the embedded memory blocks are incapable of.

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--- quote end ---

--- Quote End ---

I have now changed the entire memory structure, and it seems to be treating it like memory now. Out of curiosity how would you clear an embedded memory block? Currently it loops in the reset state until it is clear but I would like a better way.

Altera_Forum · ‎11-11-2005

--- Quote Start ---

originally posted by dcurry@Nov 10 2005, 07:52 AM

vitzh,

your vhdl coding style sucks, sorry man! compiling vhdl for simulation is much different than synthesis.

look at your code, can you draw a circuit from it? if no, then neither can your synthesis tool, or if it can, you probably wont get what you were hoping for.

vhdl is not c/c++, it doesn't execute line1, line2, etc... i looked over you code very briefly it's messy and doesn't make much sense, sorry man but that is probably what your synthesis tool is trying to tell you.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=10904)

--- quote end ---

--- Quote End ---

lol. Unfortune, but true. Its been a year+ since I have done anything in VHDL. I have now changed how the code works to try to remove race conditions and only update one variable per clock cycle. Its working better now.

My only real question now is where can I find out the critical delay path of the synthesized circuit so I can determine the max. clock frequency?

Altera_Forum · ‎11-11-2005

--- Quote Start ---

originally posted by vitzh@Nov 11 2005, 07:25 PM

i have now changed the entire memory structure, and it seems to be treating it like memory now. out of curiosity how would you clear an embedded memory block? currently it loops in the reset state until it is clear but i would like a better way.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=10936)

--- quote end ---

--- Quote End ---

Thats it, but i haven't had a single design in which i needed a memory clear.

If you keep track what bytes in the memory are valid, you just have to

reset the book-keeping pointers/counters.

Cheers, Roger