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The Nios II Mailbox is loosely based on the one currently available in the SOPC Builder as a standard peripheral. Details on the mailbox are here: http://www.altera.com/literature/hb/nios2/n2cpu_nii53001.pdf (http://www.altera.com/literature/hb/nios2/n2cpu_nii53001.pdf)
The biggest differences are the implementation in purely RAM, allow simultaneous read / write access from both sides, ability to generate interrupts when the RAM has contents and the small logic footprint. Without the interrupt capability the software must poll the RAM to see if there are contents, this "polling" feature is also supported by this RAM through address offset 1. Features: - each side of the mailbox has the ability to generate interrupts (don't need to poll) - the mailbox registers themselves are implemented in an M9K block - this mailbox design has a small footprint (184 LEs + 1 M9K vs 450 LEs for the standard mailbox) - fast transaction processing with simultaneous transactions supported - configured to use a single clock with PortA considered to be the master interface of the mailboxLink Copied
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