Overlapping tightly coupled memories?

[Altera_Forum]

Hi all, 

 I&#39;m designing a multiprocessor system. In that system, there is a cpu with 1 instruction (i1) and 2 data (s1 and s2) tyghtly coupled masters.  These masters are connected to an onchip rom (i1 and s1), and to an onchip ram (s2).  Then, there is an instruction master that is used to connect to the jtag module (see my previous post about a warning if I remove that master), and a data master that is connected to some peripherals and to a shared data memory.  SOPCBuilder do not give any warning in the bottom part of the window.  Then, when generating, I got this warnings:  <div class='quotetop'>QUOTE </div>  --- Quote Start ---  # 2005.05.23 19:47:18 (*) Master tightly_coupled_data_master_0 address range (0x830000, 0x83ffff) overlaps with master data_master address range (0x0, 0x2103fff) # 2005.05.23 19:47:18 (*) Master tightly_coupled_data_master_1 address range (0x820000, 0x82ffff) overlaps with master data_master address range (0x0, 0x2103fff) # 2005.05.23 19:47:18 (*) Master data_master address range (0x0, 0x2103fff) overlaps with master tightly_coupled_data_master_0 address range (0x830000, 0x83ffff) # 2005.05.23 19:47:18 (*) Master data_master address range (0x0, 0x2103fff) overlaps with master tightly_coupled_data_master_1 address range (0x820000, 0x82ffff) # 2005.05.23 19:47:18 (*) Generating non-optimal tightly-coupled master logic due to overlap[/b]  --- Quote End ---    What does it means and what should I do to avoid them?  Thanks for everything,  PJ

[Altera_Forum]

You can safely ignore these messages if you are happy with your frequency. 

The messages are just telling you that the CPU isn&#39;t generating the optimal address decoding logic. If you want to do the optimal, just change your address map to avoid the overlap. Put the tightly coupled memories at the high or low end of memory.