2.6GHz serial IO without transceiver

[Altera_Forum]

Hello, 

 I'm working in a project that using FPGA and high speed comparator to acquire external signals. In the design, the comparator acquire data and translate to PECL logic( equal or less than 2.6Gbps ). The output of the comparator feed to the FPGA.   We have 3 channels as described above. All the 3 channels should begin to acquire data at the same time when a external trigger happen.   Now the problem is we cannot use the trigger to make the 3 channels to work at the same time.    Is there any method to make the FPGA interface with 2.6GHz serial data without Transceiver or make the Transceiver acquire data simultaneously???

[Altera_Forum]

--- Quote Start ---   I'm working in a project that using FPGA and high speed comparator to acquire external signals. In the design, the comparator acquire data and translate to PECL logic( equal or less than 2.6Gbps ). The output of the comparator feed to the FPGA.   We have 3 channels as described above. All the 3 channels should begin to acquire data at the same time when a external trigger happen.   Now the problem is we cannot use the trigger to make the 3 channels to work at the same time.    Is there any method to make the FPGA interface with 2.6GHz serial data without Transceiver or make the Transceiver acquire data simultaneously???  --- Quote End ---  To align the receivers internal to the FPGA, you first need to get all three comparators to look at a common signal. For example, a wideband noise source, or if the analog voltage swing from a transceiver transmitter is sufficient, you can sample that with all the receivers, and transmit a pseudo-random binary sequence. The cross-correlation of the 1-bit results from the receivers will then tell you the delay between channels. From that, you can 'swallow' bits in the receiver path until the signals are aligned. Then you can go back to sampling the RF signal you were originally interested in.  Cheers, Dave

[Altera_Forum]

Thank you for your reply! 

 I think your method maybe applicable. I can use the presudo bits to allign the receiver first, and then store the data after the trigger and drop the data befor the trigger.

[Altera_Forum]

--- Quote Start ---  Is there any method to make the FPGA interface with 2.6GHz serial data without Transceiver or make the Transceiver acquire data simultaneously?  --- Quote End ---   Your problem description isn't very detailed. I understand, that you mean to actuslly sample data at a rate of 2.6Gbps? In this case, the first variant can be excluded, unless you are using external SERDES hardware, e.g. an ECL shift register. For the second variant, did you check if your FPGA is able to read raw serial data with it's Gigabit transceivers? Some FPGA families are rather restricted in this regard, e.g. limited to DC balanced bit streams.