BeMicro Max 10 - DAC 5681 Out pin problem

[Altera_Forum]

*Posting again, because first thread just became a blank page. 

 Hello,  this is my first post in this forum, so if I make some kind of mistake, just let me know.<br>  I'm trying to use the DAC AD5681 that comes with the board BeMicroMax 10, but I'm having some problems to find the out pin.  http://www.alteraforum.com/forum/attachment.php?attachmentid=9875&stc=1  I checked the board datasheet and there's no Vout pin, as you can see from the image above.  And another strange thing is that I downloaded a template about the FPGA pins and all of the DAC pins are as an output.  --DAC, 12-bit, SPI interface (AD5681) AD5681R_LDACn : out std_logic; AD5681R_RSTn : out std_logic; AD5681R_SCL : out std_logic; AD5681R_SDA : out std_logic; AD5681R_SYNCn : out std_logic;  Just for reference: https://cloud.altera.com/devstore/platform/14.0.2/bemicro-max-10-kit-baseline-design/ --source of the code template<br> http://www.alterawiki.com/uploads/b/bc/bemicrom10_getting_started.pdf --source of the image

[Altera_Forum]

--- Quote Start ---   I'm having some problems to find the out pin   --- Quote End ---   You're looking at the FPGA pin assignment details, rather than the schematic level details.  As far as the FPGA is concerned, the interface to the DAC is via output-only pins. If you find and download the schematic for the kit you are using, it should contain details on how to access the Vout pin.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  You're looking at the FPGA pin assignment details, rather than the schematic level details.  As far as the FPGA is concerned, the interface to the DAC is via output-only pins. If you find and download the schematic for the kit you are using, it should contain details on how to access the Vout pin.  Cheers, Dave  --- Quote End ---    Thanks for your reply Dave.  I already checked the DAC schematic for the kit: http://www.alteraforum.com/forum/attachment.php?attachmentid=9876&stc=1   So when I saw this schematic, I realized I need to measure the pin in the board to see the analog output, because there isn't any pin associated with the DAC_OUT in the schematic. But I thought this isn't the best way to see the output, maybe there is a way to redirect the DAC_OUT to a GPIO pin.

[Altera_Forum]

So I tried to look again in the board and I found where is the pin, there is a big pin with upper case letters DAC_OUT, the problem was the datasheet of the board doesn't talk about that. 

 Thank you again, just a begginer mistake.

[Altera_Forum]

--- Quote Start ---  So I tried to look again in the board and I found where is the pin, there is a big pin with upper case letters DAC_OUT, the problem was the datasheet of the board doesn't talk about that.  Hi! Allow me to direct you to https://cloud.altera.com/devstore/board/bemicro-max-10-fpga-evaluation-kit/ this is what we call the Design Store. If you look under this link you will find the BeMicro MAX 10 "baseline" design. Follow the instructions to download and install this design. Quartus will then be preloaded with the complete pinout for the BeMicro MAX10. You should not have to enter the pinout manually. Cheers Larry

[Altera_Forum]

--- Quote Start ---    --- Quote Start ---  So I tried to look again in the board and I found where is the pin, there is a big pin with upper case letters DAC_OUT, the problem was the datasheet of the board doesn't talk about that.  Hi! Allow me to direct you to https://cloud.altera.com/devstore/board/bemicro-max-10-fpga-evaluation-kit/ this is what we call the Design Store. If you look under this link you will find the BeMicro MAX 10 "baseline" design. Follow the instructions to download and install this design. Quartus will then be preloaded with the complete pinout for the BeMicro MAX10. You should not have to enter the pinout manually. Cheers Larry  --- Quote End ---    Yeah, I did that. This code was printed from this baseline design:   --DAC, 12-bit, SPI interface (AD5681) AD5681R_LDACn : out std_logic; AD5681R_RSTn : out std_logic; AD5681R_SCL : out std_logic; AD5681R_SDA : out std_logic; AD5681R_SYNCn : out std_logic;   If you look the DAC datasheet you see it has five input signals and just one output signal, so we can just think there is a mistake in the template given by altera.  The code need to be this way:  --DAC, 12-bit, SPI interface (AD5681) AD5681R_LDACn : in std_logic; AD5681R_RSTn : in std_logic; AD5681R_SCL : in std_logic; AD5681R_SDA : in std_logic; AD5681R_SYNCn : in std_logic;

[Altera_Forum]

--- Quote Start ---   If you look the DAC datasheet you see it has five input signals and just one output signal, so we can just think there is a mistake in the template given by altera.    --- Quote End ---   No, there is just a mistake in your thinking. The DAC has a data sheet showing its *INPUTS* and the FPGA is controlling that DAC, so it drives *OUTPUTS* that connect to the DAC inputs.  Draw yourself a block diagram and it should become clearer.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  No, there is just a mistake in your thinking. The DAC has a data sheet showing its *INPUTS* and the FPGA is controlling that DAC, so it drives *OUTPUTS* that connect to the DAC inputs.  Draw yourself a block diagram and it should become clearer.  Cheers, Dave  --- Quote End ---    Yeah, you're totally right. I understood now :D.  Thank you so much.