Can i deserialize LVDS using DCFIFO ?

[Altera_Forum]

Hi, 

 I am wondering if i could deserialize a LVDS signal using a DCFIFO block ? I've tried numerous method, but no success.  Michael

[Altera_Forum]

--- Quote Start ---   I am wondering if i could deserialize a LVDS signal using a DCFIFO block ? I've tried numerous method, but no success.   --- Quote End ---    No, not really. You might be able to perform a 8-bit to 16-bit width change or something like that, but that would not technically be deserialization then would it :)  What are you trying to do? Did you try to use the altlvds_rx component?  Here's an example of LVDS deserialization at 1Gbps  http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf  Cheers, Dave

[Altera_Forum]

Technically, isn't changing 1 bit to 16 bits possible ? if 8 bits to 16 bits is possible? 

I've tried altlvds_rx, it could only go up to 10 bits.  Michael

[Altera_Forum]

--- Quote Start ---  Technically, isn't changing 1 bit to 16 bits possible?   --- Quote End ---  Only if the underlying dual-ported RAM supports writes at 16-bit and reads at 1-bit. Even if it doesn't, you can easily write a state machine to read in 16 x 1-bit values, and then write it to one port of a RAM at 16-bits. The reader on the other side would also read 16-bits. From the top-level, this component would look like a 1-bit to 16-bit deserializer.  This however only works if the clock rate of your 1-bit data can be dealt with by the FPGA. The whole point on the hard-IP LVDS SERDES is that they operate at much higher frequency than the fabric logic elements.    --- Quote Start ---   I've tried altlvds_rx, it could only go up to 10 bits.   --- Quote End ---  So, that is all they need to do. Take for example a 1Gbps data stream (which is near the fastest the LVDS SERDES can run). If you operate the SERDES in 1:8 mode, then inside the FPGA, the parallel data is 1GHz/8 = 125MHz. If you want 16-bits or 32-bits inside the FPGA, just do that demultiplexing using logic elements.  Cheers, Dave

[Altera_Forum]

Do you think i can use the altlvds_rx at deserialize factor of 6, then go through a DCFIFO to get 12 bits? 

  Michael

[Altera_Forum]

--- Quote Start ---  Do you think i can use the altlvds_rx at deserialize factor of 6, then go through a DCFIFO to get 12 bits?   --- Quote End ---    Yes, that should be possible.  You could also do 1:8, and store 3 x 8-bit values, and write it into 24-bit RAM, then read out 24-bits, and output two consecutive 12-bit values.  Cheers, Dave

[Altera_Forum]

I don't think, that there can be a reasonable answer to the question without asking about the intended LVDS bit rate. For some reason, you are assuming rates like 1 Gbps, but why? 

 Technically, it't simple: - Fastest deserialization is provided by dedicated hardware SERDES block, for those FPGA families that have it - Second fastest option (about 400 to 800 Gbps, depending on the FPGA family) is by DDRIO double data rate registers. This method is used by Quartus software SERDES IP. It's rather easy to design similar blocks on your own, if the features of the existing MegaFunctions don't fill your needs. - Deserialization with speeds up to FPGA core speeds can be done with regular registers  I don't see, what's the particular purpose of a DCFIFO in this regard.