I have a question regarding critical path of a circuit and its effect on simulation using modelsim. Does the portion of the circuit in the critical path take more clock cycles to execute an operation? ( Is this shown in the modelsim waveform) Your replies will help me get a better insight into this. Thank you
what part are you refering to when you say critical path? is your design synchronous or asynchronous? are you doing timing simulation or RTL simulation?
I am doing RTL simulation of a memory module. It is a synchronous design. The design has an address comparator (which is a combinational circuit) connected to a memory. The simulation wave forms indicate that when there is an address conflict the memory takes 2 clock cycle for a write operation. Otherwise it just takes one cycle. I was trying to figure out where the extra clock delay is coming from since there are no registers adding that delay.
If its just RTL, then you should be able to find the extra cycle in the code or in the documentation (for an external memory controller). COmbinatorial paths have 0 delay, unless they have one specified.
