Cyclone 5 GT Dev. Kit DDR3 malfunction

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Cyclone 5 GT Dev. Kit DDR3 malfunction

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Hi all,

I am using cyclone 5 GT dev. kit which consists of both hard memory and soft memory controller. I am using the board test system provided by altera to check the functioning of DDR3's. For DDR3 A and B when the start button is pressed the read, write and total percentages is at zero percentage and when the process is stopped the percentages still remain at zero level. The number of addresses to read and write is set to maximum. I have attached the images for DDR3 A start and stop condition.

Please let me know how to debug this? Are the memories have gone bad?

Regards,

Prakhar

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