Cyclone III AS Configuration

[Altera_Forum]

Hello, 

 I am having some problems getting AS configuration working with my Cyclone III FPGA. I am using an EPCS16 for the configuration chip and the C3 is a EP3C25F324C8N on a custom board. The board has 2 10 pin headers, one that is connected to the JTAG pins on the FPGA and the other which is used to program the AS device. Using Quartus II and a USB Blaster dowload cable I can succesfully program the FPGA over JTAG. I can also program the AS device over the 10 pin header. My problem is trying to get the FPGA to configure itself from the AS device. Probing some pins I have the following sequence of events.  1. nStatus is released and begins to rise since its connected to a 10k pullup. 2. DCLK begins to oscillate. 3. After about 2 DLCK cycles nCSO (connected to AS enable pin) goes low.  I'm assuming this means that the FPGA has entered configuration mode. Now the problem is that for some reason the nCSO line goes high after about 16 DCLK cycles and then I'm guessing an error is detected and thus the nStatus pin goes low. This behavior repeats over and over since the FPGA automatically resets on a configuration error. Any ideas as to the cause of the problem?  Thanks, Andrew

[Altera_Forum]

Without a schematic, my guess is you have a bad connection on your data pin, or the clock pin has some needs to be better terminated.

[Altera_Forum]

As far as I know the FPGA reads the ID of the serial config device first. If the FPGA refuses to read the configuration data from the device then there might be an error when reading this ID. Maybe you should probe the DATA pin of the EPCS and see whether valid data comes out of the device.

[Altera_Forum]

Thanks for the suggestions. The schematic is identical to the design referenced in Figure 10-29 in the Cylcone III handbook (http://www.altera.com/literature/hb/cyc3/cyc3_ciii51010.pdf) on page 10-58. I checked to see if the FPGA was issuing the command to get the device ID from the EPCS16. To check to see if the connections were ok I assigned each of the pins (DCLK, ASDO, and DATA) a clock output from the FPGA and measured it on the JTAG header pins. The clocks looked ok except for on the ASDO pin where there was a lot of ringing. 

(http://www.altera.com/literature/hb/cyc3/cyc3_ciii51010.pdf)  This figure shows DCLK in yellow, ASDO in green, and nCSO (the EPCS16 chip enable) in purple. It looks like the ASDO pin is trying to issue a command but it seems like something is wrong with the trace. Does this seems like an accurate diagnosis? Are there any software settings in Quartus that have to be set for AS to work? Unfortunately, I only have 1 board to work with until tomorrow so I can't see if the problem is reproducible. http://www.stanford.edu/%7Eadprice/1.bmp

[Altera_Forum]

Well those signals look really bad. However, that may be due to two reasons: 

 1 - You are measuring at the JTAG header rather than at the FPGA or serial configuration device. Measuring in the middle of the trace will often give you garbage.  2 - The rise and fall times on your ASDO and nCSO signals are terrible. What kind of scope probes are you using? Any capacitance in the probe will affect what you see (sometimes dramatically). For what you're looking at, you really need a probe in <10pF range.  How are your MSEL pins configured? Looking at the Cyclone III datasheet, I would use 0010 or 0011 (depending on your voltage) for slow configuration. Also, yes you do need to specify the configuration scheme in Quartus. This is found by clicking on the "Device Options" button on the device settings page.  Jake

[Altera_Forum]

I wonder, if you should first remove a bandwidth limitation from oscilloscope channel setup. It don't looks like a real signal, to my opinion.

[Altera_Forum]

I agree that the signals look pretty bad, but I don't know if it's a measurement problem with my oscilloscope. I have 9pF probes and when I measure signals from the JTAG header that programs the FPGA directly they look ok. I guess my question is, do you guys know what might be causing these bad signals? Has anyone had personal experience with the setup I described (JTAG and AS)? If so, are there issues in layout or component selection I should be aware of? 

 Thanks, Andrew

[Altera_Forum]

Oh sorry Jake...My MSEL pins are 0010 for the slow AS configuration. I checked the device setting in Quartus as well and even with it set correctly I still have problems.

[Altera_Forum]

I definitely doesn't look like a normal oscilloscope probe, rather like a 20 MHz bandwidth setting. Fast and slow AS are only involving different POR delays and should be both O.K.

[Altera_Forum]

Perhaps I am mistaken as I have not worked with Cyclone III. But on the Stratix II devices, Fast and Slow control the speed of the active serial clock (40MHz vs. 20MHz). The POR delay is controlled via another pin. 

 Jake

[Altera_Forum]

I believe in the Cyclone III the POR delay is controlled by the AS setting (fast or slow). The clock is supposed to stay at 30 MHz for either setting. I'll check my scope again to make sure it's not a measurement issue.

[Altera_Forum]

To prove my oscilloscope is configured correctly I've used the same probe to measure the output of a 50 MHz crystal oscillator I have on the board. Here is a plot of that output. 

 I agree that the rise and fall times are pretty large but that must be from some other capacitance. As I mentioned, my circuit is identical to Figure 10-29 in the Cyclone III handbook. Any ideas what's going wrong?  http://www.stanford.edu/%7Eadprice/3.bmp  http://www.alteraforums.com/forum/www.stanford.edu/%7Eadprice/3.bmp

[Altera_Forum]

May be you have assembled caps of about 470p to 1 nF instead of 10 pF?

[Altera_Forum]

Good idea, but no luck. I removed the caps and the signals looked exactly like the previous plot I posted. Correct me if I'm wrong, but DCLK looks ok, it's just the rise time on nCSO and the ASDO lines that look bad, right?

[Altera_Forum]

--- Quote Start ---  Correct me if I'm wrong, but DCLK looks ok, it's just the rise time on nCSO and the ASDO lines that look bad, right?  --- Quote End ---   DCLK may be regarded OK, but it doesn't look like a FPGA output signal, the other signal are beyond acceptable specifications. A hardware engineer should be able to see the reason with the board at his fingertips, but not from a distance.

[Altera_Forum]

Well, if anyone still follows this thread, I fixed my problem. The culprit was the clamping diodes (see reference circuit in handbook). I'm not really sure why that fixed it though. Maybe they were backwards, or maybe they were the wrong type of diode. If I get bored I might play around with it.

[Altera_Forum]

Oh sorry, I guess I should clarify...I removed them

[Altera_Forum]

From the capacitance estaimation, you seem to have used zener diodes or power rectifiers. Small signal schottky diodes would be correct.