Cyclone IV nCONFIG pin is not stable

[Altera_Forum]

Hello everybody, 

 I have a strange hardware problem and hope somebody can help me.  I made two Cyclone IV testing boards. Both have the same problem: After power on, everything seems ok. The nCONFIG pin is stable at about 2.9 V. My VCCIO = 3.0 V for all banks. After some time, about several seconds to several minutes, the nCONFIG pin voltage collapses to a much lower level. At first it was around 0.7 V. Moreover, this voltage is not stable. It jumped between about 0.7 V and 2.5 V randomly and quickly. After a lot of searching and trying we think that it should lie in the bad reflow soldering process, meaning that the FPGA chip is not well soldered at some pins, or there might be a weak and not continuous short circuit (contacting R = about several KOhm) between nCONFIG pin and the nearby GND pins. Therefore we sent the two boards back to the soldering compnay and they heated the boards again with a longer time and the highest acceptable temperature for the FPGA.  After the re-heating, it gets better: the nCONFIG voltage jumps now between about 2.0 V and 2.8 V, sometimes as low as 1.5 V, but not yet reaches the digital low level. So the board can work, meaning we can configure the FPGA with JTAG and program the EPCS chip. Also before the re-heating, the FPGA could be configured via JTAG and EPCS before the nCONFIG voltage collapsed. Now it can be configed at any time. But I am afraid after some time, the nCONFIG voltage might drop and below the logic low threshold.  After a detailed analysis again, I think the nCONFIG pin has a low resistance to the GND. Maybe it is a dirt contacting the pins and causes a contact resistance now around 20 k. The reasons that I come to this thought are the following phenomena besides what I described above:  1. The voltage only goes low.  2. The voltage is always good when the chip is cold. If the chip is getting warm (the temperature is still below 30 °C), it takes much less time, sometimes only 5 - 10 seconds, that the nCONFIG voltage collapses. Maybe the higher temperature causes some expansion and makes the "short circuit" resistance to be contacted.  What is strange is that both boards have almost the same problem. If it is because of a dirt underneath the chip, it should be highly impossible that such random located dirts could cause the same problem in two boards.  I also checked my circuit to see if my circuit has problems, but cannot find. In order to isolate the possible problems, for one board at first, I only had the FPGA and the most basic components (power supplies, clock circuit, JTAG, EPCS chips) on the board to ensure the basic operation of the FPGA. Several other irrelavent chips (SRAM, ADC, etc.) are also present. The nCONFIG pin has ONLY a 10k Ohm pull-up R connected to the VCCIO. The problem is still there!  In the Altera user's manual, it says that nCONFIG keeps low before all power supplies are good. I measured all three power supplies. They are all good: VCCINT = VCCD_PLL = 1.2 V with about 20 mV peak-to-peak ripples VCCA = 2.5 V with about 10 mV peak-to-peak ripples VCCIO = 3.08 V with about 30 mV peak-to-peak ripples  The FPGA type is EP4CE115F23C8N, 1.2V core. The clock is 50 MHz generated with an silicon clock oscillator.  For the configuration, I use JTAG and AS. MSEL[3:0] = '0011'.  Does anybody know this problem? Can anybody help me? What could this problem lie in?   I appreciate for any hints!  Michael

[Altera_Forum]

Hi, 

have you also monitored the VCCIO when the nConfig drops, i.e. is the VCCIO not only measured at power up but during Operation as well? Have you also checked that either all physically connected Pins are declared and assigned in QII or - my Option I choose - the "tristate unused Pins" opion is set in QII - Standard is that all unused Pins are driving GND, sometimes this can result in incompatibilities with the board layout in Terms of excessive current consumption, either heating the FPGA or overloading the power supply line..

[Altera_Forum]

Thank you Carlhermann!  

 I observed all power supply voltages before and after the nCONFIG problem. All voltages are stable. I hope to find some synchronized changing between nCONFIG and any other signals, but have found nothing.  Your suggestion about the undefined pins is definitely very helpful. During the testing, we did let many pins undefined. During the testing process and more functions are added, more and more pins are defined. This could be a source of the problem because the nCONFIG signal suddenly gets correctly stable since the second debugging day after the re-heating, without any special actions of us.  Based on this consideration, we generated an empty project with only a defined clock pin and one output pin. All other pins are undefined. We loaded this project down to the FPGA and also to the EPCS chip. We let the system run this empty project for a very long time, but the nCONFIG pin voltage always keeps high and stable.   Till now, two whole days have past and the nCONFIG voltage always keeps stable. No problem appears any more. This is good so that we can process our test. However, it is bad that we still don't know the cause of the problem. We are afraid that this problem will be present again in our new system versions :-(

[Altera_Forum]

I agree that the worse stuff than a non-working board are those "magical self-healing" ones. These tend to fail operation later and that is annoying. Nevertheless I'd suggest to work on with your code and check the schematic and layout once again prior production of new boards. You should also check the pinout of the FPGA in the schematic to match the pinout file from ALTERA. Just as a sidenote - if you used the symbols provided by ALTERA you might find it worth checking these as well as these are generated by humans as well and while it is very unlikely these can also include a mismatch.  

 Hope you have a hardware troubles free time now :)

[Altera_Forum]

Thank you again, Carlhermann. 

 Yes, it is always important to check the circuit according to the user's manual, although it is time-consuming and annoying.  Unfortunately I am not very familiar with QII and HVDL. My colleague is doing the SW stuffs. However, I will talk with him and forward him your comments.   Sonner or later I will have to become a Qii expert any way.  Enjoy the nice summer in Germany:-)