Cyclone V SoC HPS2FPGA AXI : processor hangs on non 64 bit aligned reads

[Altera_Forum]

I am trying to access FPGA registers (as 32 bit words) from the HPS through the HSP-to-FPGA Brigde (not the lightweight bridge), which is configured for 64 bits. 

This works when reading 64bit aligned addresses (eg 0xC000 0088), but not for 32 bit aligned addresses such (eg as 0xC000 008C), in which case the processor seems to hang.   This is the case in both Uboot and in Linux (so I am currently concentrating on Uboot to keep things as simple as possible). The Uboot (and preloader) are generated with the 13.1 EDS + some git patches (socfpga_v2013.01.01-rel branch) based on the FPGA handover files.  If I do the same using the (32 bits) lightweight bridge everything works fine. We already tried configuring 32 bits on the normal bridge as well but it still did not work (but when using the normal bridge it is always 64 bit between the L3 interconnect and the bridge, which with the lw bridge this is also 32 bit so it is still different).   Did anyone already got this working and maybe encountered something similar ?  The Cyclone V Device handbook, in chapter 5 HPS-FPGA AXI bridges around table 5.3 there is an explanation about the fact that enabling ECC in the L2 chache requires 8 byte alignment. I am not sure this could be related to my problem (I would hope the cache does this automatically) , but I wanted to try and disable ECC or the L2 as a check.  However, I found that # define CONFIG_SYS_L2CACHE_OFF 1 is completely ignored by uboot when building Uboot for the cyclone V.  Anyone any suggestions on how to control either the ECC or L2 cache ?  Thanks