Cyclone2 configuration, CONFIG_DONE stuck low

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EP2C5 will not exit the Active Serial Configuration Stage. Circuit is exactly as Fig. 13-7, page 13-20 in Cyclone2 Device Handbook, Vol. 1 for a single device. Configuration device is EPCS4. Using USB Blaster Quartus II v9.1 seems to program and verify the EPCS4 successfully with the .pof file. I followed the FPGA Configuration Troubleshooter suggestions for CONFIG_DONE not going high, but these do not help.  

 Setup: All VCCIO = 3.3Vdc.  All VCCINT = VCCPLL = 1.2Vdc.  MSEL[] = 00. Confirmed with VOM. All pull-ups are 10k for AS configuration (per Fig. 13-7).  nCE pull-down is 10k. (Measures 0.03Vdc when powered, so seems low enough) All pull-ups and pull-down for the JTAG connections are 1k (per Fig. 13-22) Each VCCIO and VCCINT pin is bypassed with .1uF. 3.3Vdc and 1.2Vdc produced by LDO regulators and bypassed with >20uF each.  Symptoms: 1. VCCINT comes up in <50 us and is solid.  2. nCONFIG goes high when VCCINT powers up. 3. nSTATUS goes high 100ms after nCONFIG goes high. This seems odd to me, because FIG.13-7 and Table 13-7 show the tCF2ST1 (delay time between nSTATUS going high after nCONFIG) should be 40us max.  4. nSTATUS toggles every 37ms perpetually once it goes high, low duration time is 40us.  5. nCSO goes low when nSTATUS goes high, but it toggles high and low every 37ms perpetually, high duration time is 40us. 6. CONFIG_DONE never goes high. 7. There are lots of DCLKs and DATAO pulses while nCSO is low.  Second problem: The EP2C5 fails to do anything it should after a JTAG config. This board is also wired for JTAG configuration as per Fig. 13-22, page 13-55, same document. Programmer recognizes the EP2C5 with AUTO DETECT. The message reports success after JTAG config, taking only 1 second to download.   Also, I don't know if this is relevant with JTAG config, but I did enable INIT_DONE output. What seems strange is that there is a continuous output from it, 200.0us wide pulses at about 37ms intervals. These are present all the time and during the time JTAG is supposedly going through a config cycle as well.  All EP2C5 pins are beautifully soldered as inspected with a microscope.  I don’t know what else to try or look at. Is it time to pull the EP2C5?