I am trying to interface a EP2SGX90EF1152I4 to a GS8342T36AE (36Mb SigmaCIO DDR-II Burst of 2 SRAM). I developed my own interface, which was not hard. I have a functional simulation with the vendor model, which works great. The problems start when I try to do a post place and route timing simulation. Everything looks good, including the write data going to the RAM and read data coming back, however, the Altera DQS module, which is supposed to generate my internal read clock from the CQ and CQ_N signals, always outputs 'x'. As a result, the read data is never clocked in. When I try a post place and route timing simulation of the Altera DQS module stand-alone, it works fine. When I try the design in hardware, data is read from the RAM, so the DQS module must be producing a clock, however, the data is always wrong. Data that I write is always read back at a different nearby address.
Any thoughts?
