Discrepancies between datasheets and technical documentation regarding FPGA configuration.

[FFmine]

About Arria V data sheet 

https://www.intel.com/content/www/us/en/docs/programmable/683022/current/active-serial-as-configuration-timing.html

Note 105 is as follows.

105 To evaluate the data setup (tSU) and data hold time (tDH) slack on your board in order to ensure you are meeting the tSU and tDH requirement, Intel recommends following the guideline in the "Evaluating Data Setup and Hold Timing Slack" chapter in AN822: Intel FPGA Configuration Device Migration Guideline.

However, AN822 mentioned tDSU, but tSU was no there.

https://www.intel.com/content/www/us/en/docs/programmable/683340/current/evaluating-data-setup-and-hold-timing-slack.html

Is tDSU in AN822 just a misspelling?

[FvM]

IMHO no misspelling, just a different valid symbol for the same measurement.
tDSU = data setup time
tSU = setup time

[FFmine]

Thanks for your reply

I think so too.
Your opinion has gave me confidence in my thinking.
But tDSU and tSU has different value in Arria V data sheet.
tSU value is 1.5nsec at AS configureation section and tDSU value is 5.5nsec at PS configureation section.
And, these paramaters has diffarent memo as follows.
tSU : Data setup time before the falling edge on DCLK
tDSU: DATA[] setup time before rising edge on DCLK

I realized the probrem is an explanation method for tSU is tDSU in AS configurasion section.

Thank you for your help.

[TingJiangT_Intel]

Glad to know your problem has been addressed. Any updates please let us know.

[TingJiangT_Intel]

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