FIR Filter Design using Altera_MULT_ADD_13.1

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

FIR Filter Design using Altera_MULT_ADD_13.1

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Hello Every One,

I am working on FIR Filter Transpose architecture design using altera_mult_add_13.1 (dsp) megafunction in verilog and I am using Altera Quartus 13.1 edition.

When I am simulating the design it is showing FIR outputs as undefined (UUUUUUUUU....) and displaying error message that "altera_mult_add is not bound."

One observation is there is no simulation model for this "altera_mult_add" IP in Altera Quartus 13.1 Web edition. Does any one getting the same error.

Could any one help me How to get simulation model for this "ALTERA_MULT_ADD" IP and Simulating the design using this IP.

Thanks in Advance.

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