How to enable dual core cortex A9 mode of Cyclone V?

[Altera_Forum]

I have used Cyclone V in Single Core configuration but i don't know how can use it in Dual core mode. I have checked the reference manual where i can only see HPS Info Register. This register indicates if CPU1 is available in MPU or not and it is read only. How can enable CPU1 ? 

 Thanks, Naveed

[Altera_Forum]

Hi, 

 By default CPU1 is held in reset on boot. You can pull it out of reset by changing the correct bit in the mpumodrst register in the Reset Manager, but...  It's not that simple. You need to take care of a bunch of things to ensure that the two cores don't conflict with each other and to setup CPU1 (core1) before releasing this core from reset. A simple thing that I "think" you can do is just point cpu1's start address (cpu1startaddr) at a location that CPU0 won't bother and then populate that location with a tiny neverending loop.  Anything beyond that would require setting up vectors, etc. Basically, everything that's mentioned in ARM's documentation on the Cortex-A9 in this respect.  As I stated previously, it's not that simple.  Cheers and Good luck!  slacker

[Altera_Forum]

Thanks slacker for replying. Whenever i try to pull CPU1 out of reset by writing mpumodrst my system throws "Target Message: Could not determine target state". I am using DS-5. Do you have any idea what might be causing this ?

[Altera_Forum]

The second core jumps to an unknown location when first core sends an IPI to schedule a task. Please reply if anything comes to mind.

[Altera_Forum]

The second core does not execute any instruction when the first core send an IPI for task scheduling. Second core is stopped at instruction "S:0xFFFF0100 : LDR sp,[pc,#-164] ; [0xFFFF0064] = 0xFFFFE6A4". So in reality the first core bear all the load. The same code is working fine on i.MX6 on 2 cores. What could be the difference? 

 P.S. I am using DS-5.

[ALTERA-INSUPPORT22]

@Altera_Forum  Did you find the solution? I am also facing the same situation. 

I combined two bin files, core 0 also taking core 1 out of reset, but the problem is core 0 program counter is fine and in range after 0x60000 showing it work fine as in linker its entry point is 0x60000 but core 1 program counter goes to 0xFFFF0004 but its entry point in linker file is 0x100000

[ALTERA-INSUPPORT22]

I am working on intel cyclone 5 hps I have two cores in a processor Core 0 core 1, I want two code to run on two different cores core 0 and core 1 in bare metal .

When I run in jtag mode it works, for jtag i first debug using core 0 where i take core 1 out of reset it, than debug core 1 usign jtag it work

BUT, When i want to run both core usign qspi it only run core 0 not core 1

Here is the step i followed

Firsly, loading preloader
quartus_hps -c 1 -o P preloader-mkpimage.bin

I make an image from bin file of core 0 and place it to qspi

mkimage -A arm -O u-boot -T standalone -C none -a 0x00060000 -e 0 -n "baremetal image" -d core0.bin core0.img

quartus_hps -c 1 -o P -a 0x00060000 core0.img

I make an image from bin file of core 1 and place it to qspi
mkimage -A arm -O u-boot -T standalone -C none -a 0x00100000 -e 0 -n "baremetal image" -d core1.bin core1.img
quartus_hps -c 1 -o P -a 0x00100000 core1.bin

When i restart board only that code work which is in core 0, core 1 code not executing

I am setting cpu1startaddress 100000 apart from that in the code of core 0 also i am using alt_qspi function to to place bin file data in ddr, 

I want to run in smp mode so I also set required aux_control_register smp and fw bit as stated in tech ref manual  

alt_qspi_read((uint32_t *)BL_START/*ddr3 address*/, 0x100000/*qspi address*/, 0x40000);

In linker/scat file core 0 entry point is 0x60000 and

linker/scat file core 1 entry point is 0x100000