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How to use Signal tab to verify signal PHY Lite for Parallel Interfaces FPGA IP

phuongnn0
Beginner
282 Views

Hi,
I am new for FPGA
I am using
Arria 10 - 10AX115S2F45I1SG
My design uses PHY Lite for Parallel Interfaces FPGA IP.
When I enable signal tab in Asembler.

phuongnn0_0-1745202286476.png


I have problem when synthesizing

Error(17044): Illegal connection on I/O input buffer primitive dynamo_0|dynamo_0|phy_lite_dq|phylite_0|core|arch_inst|u_phylite_io_bufs|data_io_buf_gen_grp[0].data_io_ibuf_gen[0].u_twentynm_io_ibuf. Source I/O pin dynamo_0_conduit_end_dq[24] drives out to destinations other than the specified I/O input buffer primitive. Modify your design so the specified source I/O pin drives only the specified I/O input buffer primitive.

 

This error would not appear if I did not "enable signal tab logic analyzer"

Please help me fix this problem. Thank you very much.

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sstrell
Honored Contributor III
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You are most likely tapping a post-fit node in your design that cannot be tapped.  Look over the Node List in your Signal Tap file and see if you can tap either a pre-synthesis version of the node or another signal that feeds into the node you want to look at.

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Kenny_Tan
Moderator
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Another suggestion is to follow the PHYlite hardware simulation in https://www.intel.com/content/www/us/en/docs/programmable/683384/current/an-747-altera-phylite-for-parallel-interfaces.html


Since this is something we already developed and works.


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Kenny_Tan
Moderator
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Kenny_Tan
Moderator
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Is there further question? If no, we shall close this thread.


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phuongnn0
Beginner
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Hi  Kenny_Tan
Thanks for your reply.
I am new. The examples you shared are quite brief about using signal tab
Please send me a tutorial or step by step example on using signal tab for arria 10

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Kenny_Tan
Moderator
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Here you go, https://www.youtube.com/watch?v=R8vUERKTDzg


I attached a screenshot below for you to take note on the postfitsignaltap. You should watch the video completely.




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phuongnn0
Beginner
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Hi  Kenny_Tan,
Thank for reply.
You can close this thread

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