IIR filters in FPGA

[Altera_Forum]

The problem is as follows: 

- we have a need for a low pass IIR filter (minimal delay - low order) - used type of filter is Elliptic - generation of the filter is in Matlab fdatool - characteristics of the filter are - 16kHz sample freq, cutoff at 2kHz, passband ripple 0.05dB, stopband -60dB - implementation in VHDL - fixed point arithmetics, generated by FDATool ------------------------------------------------------------------------- - the minimum order filter designed by fdatool is 14 - quantization settings:  * 64bit coefficient word length * input word length 16,fraction length 15 * output word length 16, avoid overflow * section input/output word length 16 * round towards nearest(convergent) * product/accum. mode - Full precision * state word length 16, fraction length 7, avoid overflow * overflow mode - Saturate FPGA used is Altera Cyclone III  The filter generated by the FDATool is unstable and does not perform as designed. The only one stable enough is a 4th order filter which is no good to us since it decays too slowly. My question is: is there a way to make the filter stable by any means of quantization parameters? Or is it better to use a DSP processor and run full floating coefficients? Has anyone done this in NIOS2 processor?  Thank you in advance

[Altera_Forum]

For fixed point arithmetics it's recommended a Type III structure (Transpose-Form IIR Filter Structure) or a cascade of second order stages (as suggested by fda tool). I have implemented stable 13-order filters using 8 bits just with a Type III Structure.

[Altera_Forum]

Either I have missed it somehow or I don't have a Type III structure, just Type II. What Matlab are you using? I have v7.3

[Altera_Forum]

@milosd 

 Most DSP related textbooks introduce IIR filters with there normal form implementation that can directly be derived from the z-domain transfer function equations.   This kind of normal form implementation is however very sensitive to 1) the coefficient values and 2) the rouding or truncation effects. The finite word length effects give rise to digital noise, but even more important limit cycle oscillations.   One often used solution is to implement the IIR filter as a cascade of second order sections as parrado rightly introduces. But it is well known that second order sections can also have limit cycle oscillations.   For hardware implementation on chip or on FPGAs "Wave Digital Filters" (WDF) are the best solution. Due to their structure Wave Digital Filters are less sensitive to their coefficient values. So you can realize them with much shorter coefficients. (64 bit coefficient values are really very long.). Also Wave Digital Filters are the only class of IIR filter implementations for which it has been mathematically proven that there is absence of limit cycle oscallations.   Try using WDF's it is the best and in FPGA resource terms the cheapest you can get!

[Altera_Forum]

Type III is same to Direct II Transpouse.

[Altera_Forum]

As I need a IIR filter and there is no longer a ALTERA IP I have had a look in the forum and found SANMAO's interesting comment. You say WDF is best for implementing in FGPA. Can you give me a hint how to design the filter. I don't have MATLAB but of course can purchase a tool. Nevertheless it would be fine to have the right one. 

 Thanks

[Altera_Forum]

Hi sanmao, 

Do you know the example code for wave digital filter implementation? Thanks.

[Altera_Forum]

I work as a consultant and have done several IIR filters.. I typically use biquad sections to implement the filter and simulate the results to validate stability that quantization of the data path doesn't doesn't cause a divergence between the hardware and full floating point matlab simulations.. 

 I have found that depending on the filter characteristics, the number of coefficient bits becomes critical. I typically use the Direct Form I method for fixed point and scale the result of the summation at each stage based on my coefficients to maintain data path bit width.  A good website to see the different forms of biquads is www.earlevel.com/main/2003/02/28/biquads/  What I have found that I'm able to do that the generated IP's are unable to do effectively so far, is scale my hardware reuse based on the performance requirements of the system. I always make my coefficients programmable, and usually have a state machine that I can work through either a single MAC, or Biquad stage and have a programmable (within limits) number of stages the data is ran through.. This give's software the ability to change the filter characteristics of the system without re-building the FPGA.  I primarily work with Verilog instead of VHDL, but if you would like some help, send me a message and we'll get in touch.  Regards  Pete