Interfacing the FPGA to a micrcontroller

Altera_Forum · ‎02-22-2010

I am designing a circuit that is to carry out a correlation funciton on two sets of input waveforms. The value after the calculation is stored in D flip flops. It is update continuosly as the calculation proceeds.

The specification requires me to interface the circuit to a microcontroller. I am struggling with how to achieve this. Usually there would the readNot, chipSelect, Address bus & Data bus coming over from the Microcontroller. How do I make the circuit that I turn on the tri state buffers only when the Microcontroller wants to get something from my circuit?

Also I need to have registers that shall store which of the calculated values have been Read by the Microcontroller already so that when all the values have been read the DataAvailable signal shall go low.

Any advice on this topic is Very Very highly appreciated. Any link that can help me in understanding how to do this is also very appreciated. :)

Altera_Forum · ‎02-22-2010

Hi,

depending on your requirements you have a number of options,

a) Your can present the micros address and data bus, rd/wr and cs signals to the fpga, and simply decode them in the fpga, depending on how much resources you require. Simply memory mapping the fpga into the micros address space. Doing a search on the topic interfacing 8051/AVR/PIC to fpga should produce some suitable hits.

b) You can just place an I2C slave core on the fpga, and with just 2 external lines from the micro (SDA and SCK), you can configure hardware registers in the fpga via (Master) I2C code on the micro. Alternatively, you could do the same using an SPI slave core. There much I2C code availabe for free on the net. Suitable cores are available for free from Opencores.org.

I hope that helps.

Herbx

Altera_Forum · ‎02-22-2010

Hi,

You can set the output port to high impedance when the chip select from the MCU is high/low(depends on the active level). For example:


reg  reg_calc_data;
wire  databus;
assign databus= (chipselect) ? reg_calc_data : 8'bZZZZZZZZ;

For the data availability you can use a dual port fifo ram.

Here is some example http://www.asic-world.com/examples/verilog/asyn_fifo.html

Quartus has a build in Megafunction for FIFO memory. Take a look at the megafunctions documentation.

Best regards,

VT