Multiplication on floating point format

[Altera_Forum]

question: in order to use the quartus ii to do the calculation (multiplication) of floating point, may i know what is the format type used in quartus ii to convert the floating point value to binary? thanks

[Altera_Forum]

Altera have megafunctions for doing floating point arithmatic, so there is no conversion. There is a floating to fixed point megafunction too if you want to do fixed point instead.

[Altera_Forum]

Quartus uses IEEE standard float format, as described in detail in the altfp_xxx Megafunctions manual.

[Altera_Forum]

Here is the link: 

http://www.altera.com/literature/ug/ug_altfp_mfug.pdf

[Altera_Forum]

Thanks everyone.:o 

 I was plan to use cyclone II as family devices and do a simple twice multiplication between twiddle factor and any input values. I am using Quartus II ver.8.1 currently. Is it possible to do so?:(

[Altera_Forum]

floating point is never simple. The floating point mega functions are quite large and have a few clocks of latency. But a couple inside a cyclone 2 should be fine.

[Altera_Forum]

I also using NIOS II to boot in the program into DE2 Board. can it work?

[Altera_Forum]

Yes - you can do a lot with FPGAs.

[Altera_Forum]

Tricky, I am new with MegaFunction. What is the different between the VHDL coding in Megafunction and normal VHDL that I usually use in the lectures? How should i start my VHDL of floating point multiplication program?

[Altera_Forum]

A megafunction is a block of Altera IP. Most of it is written in VHDL and/or verilog, so you can simulate it alongside your own bits of HDL. You can create megafunction blocks via the Megawizard in the tools menu. The megawizard will create VHDL files with all of the setup parameters already specified (or if you are more confident, instantiate them straight from your VHDL - you can get all the parameters in the megafunction help section). These can be instantiated in your VHDL. You just treat them as a black box.

[Altera_Forum]

I still can't get it. is it first need to create a new custom megafunction variation?

[Altera_Forum]

you need create an interface to the megafunction, but the megafunction itself already exists in the altera libraries.

[Altera_Forum]

Sorry to ask this, how to create an interface to the megafunction? I never use this function.  

for example this is my previous codes: library ieee; use ieee.std_logic_1164.all;  library floatfixlib; use floatfixlib.fixed_pkg.all;  entity my_mult is  port (  clk : in std_logic;    a,b : in sfixed(3 downto -4);  c : out sfixed(7 downto -8)  );   end entity my_mult;   architecture rtl of my_mult is begin    mult_proc : process(clk)  begin  if rising_edge(clk) then  c <= a * b;  end if;  end process;

[Altera_Forum]

you are using fixed point, not floating. There is no need to instantiate floating point megafunctions. 

 But the megawizard creates the files and component declarations you need. You just connect it up with a port map  ie.   my_inst : some_entity port map ( clk => clk, input1 => signal1, input2 => signal2 ....etc );

[Altera_Forum]

Yes the code above is doing fixed point. i also doing for floating point.

[Altera_Forum]

how are you doing floating point? the floatfixpkg.float_pkg.all will not produce very good hardware results.

[Altera_Forum]

Yeah... i plan to do new program for floating point application. But the problem is i still don't know how to start the programming. i still figure it out. Do you have any sample coding for others application like addition or subtraction? what library to include and the method of writing the code?

[Altera_Forum]

What files should added while create a new project wizard?

[Altera_Forum]

You need to create VHD files from the mega wizard. You should also get a .cmp file, that contains the component declaration. Copy and paste this into your design file, and conecct up the ports something like this: 

  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity fpadder is port ( ------------------------------------------------------------ --Clock and reset ------------------------------------------------------------ clk : in std_logic; a,b : in std_logic_vector(31 downto 0); c : out std_logic_vector(31 downto 0); ); end entity; architecture rtl of fpadder is component my_fpadder PORT ( clock : IN STD_LOGIC ; dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; begin inst1 : my_fpadder port map ( clock => clk, dataa => a, datab => b, result => c ); end rtl;   Then include your source file and the megawizard generated .vhd file in your project.

[Altera_Forum]

Thanks Tricky. I'll figure it out. Thanks for your help.