Nest if statement in case statement

[Altera_Forum]

Hi, 

 Is it customary and synthesizable to use nested 'case' statement inside the 'if' statement?  Tnx

[Altera_Forum]

--- Quote Start ---  Hi,  Is it customary and synthesizable to use nested 'case' statement inside the 'if' statement?  Tnx  --- Quote End ---    No it is not , but it dosent make any sense why would anyone use "case" inside a "if" when you can use elsif multiple times .  for example:  Interfacing_ADC_DAC: PROCESS(sys_clk, reset_n) BEGIN IF reset_n = '0' THEN  ADC_data_A <= (others=>'0');  ADC_data_B <= (others=>'0');  --  DA <= (others=>'0');  DB <= (others=>'0');  --  LEDG(1 downto 0) <= (others=>'0');    -- 1st Condition -------------------  ELSIF SW(4 downto 2) = "011" THEN   LEDR(2 downto 0) <= "001";  ADC_data_A <= ADA_D;   ADC_data_B <= ADB_D;  ----------------  -- DAC is connected to an Up-Counter   DA <= Count;  DB <= not(Count);    -- 2nd Condition -------------------  ELSIF SW(4 downto 2) = "010" THEN   LEDR(2 downto 0) <= "010";  -- ADC output is connected directly to DAC   DA <= ADA_D;   DB <= ADB_D;    -- 3rd Condition -------------------  ELSIF SW(4 downto 2) = "001" THEN   LEDR(2 downto 0) <= "100";  -- DAC is connected to a NOC output  DA <= nco_sin_out + OFF_set;   DB <= nco_sin_out + OFF_set;    -- 4th Condition ----------------<< FIR Filter  ELSIF SW(4 downto 2) = "101" THEN   LEDR(2 downto 0) <= "100";  -- ADC is connected to FIR Filetr  ast_sink_data <= ADA_D;   ADC_data_B <= ADB_D;  -- DAC is connected to a NOC output   DA <= ast_source_data;   DB <= not(Count);  ------------    END IF; END PROCESS;

[Altera_Forum]

Tnx for quick response. 

The "No it is not" answer refers to customary or synthesizable or both of them? Tnx

[Altera_Forum]

--- Quote Start ---  Tnx for quick response. The "No it is not" answer refers to customary or synthesizable or both of them? Tnx  --- Quote End ---    unfortunately I disgree with the "no..." from fpga_guru011. The main differences are to do with priority issues. the case statement is equivalent to multiple parallel ifs.  Most of everyday code is made up of " if" or "case" inside each other.  if rising_edge(clk) then if enable = '1' then case .... when .... if... end if; end case; end if; end if;

[Altera_Forum]

--- Quote Start ---  Tnx for quick response. The "No it is not" answer refers to customary or synthesizable or both of them? Tnx  --- Quote End ---    There is no problems using Case inside If or If inside case. It depends what you are doing, and what you expect from the circuit.

[Altera_Forum]

Thanks to all :)