Hi,
I'm trying to determine whether the serializers and deserializers for a Stratix IV GX can be driven from the same PLL, but with different phases of the VCO, without using the DPA circuits.
I am receiving and transmitting parallel data (at 1Gbit/sec) from external devices that use a common clock, but there is skew between the different devices data busses (but not within the bus). Thus I need to drive the SERDES to match the external devices setup and hold times, and that requires that I use different PLL outputs (c0, c1 etc) to drive the SERDES, and other divided outputs (c2, c3 etc) for the word size registers.
The device handbook implies I can do it, but I haven't had a successful compile yet. This is of course all happening against a background of malfunctioning ALTLVDS_TX and ALTLVDS_RX MegaWizards and (just now) the fitter crashing out.
Any comments welcome! I'm using 10.0 SP1.
