QSYS and JTAG Debugger

[Altera_Forum]

I have a design I've built in QSYS using a 16-bit bus. I'd like to include the JTAG to Avalon Master in my design so that I can do a quick system-level check using TCL commands before handing it off to a software guy. 

 Before building this relatively complex design, I took a half a day to build and test a simple 8-bit design on an eval board. This is an incredible tool!  However, I'm stuck getting the JTAG Master into my 16-bit design. QSYS complains that the JTAG master has an 8-bit symbol width, while all my slave devices have 16-bit widths.  Is there a 16-bit version of the JTAG Master, or some "magic" 8-bit to 16-bit bridge I can put in?  Thanks in advance!

[Altera_Forum]

The JTAG-to-Avalon-MM master has a 32-bit data bus. See Chapter 18 

 http://www.altera.com/literature/ug/ug_embedded_ip.pdf  Under SOPC Builder you do not have any option to change the bus width. I assume that under Qsys its the same.  The Qsys system builder should insert width adapters.  If it does not, just create your own components with 32-bit widths, and generate two 16-bit transactions if all byte-enables are enabled. This is what I do to make 16-bit SRAM look like 32-bit SRAM.  Cheers, Dave

[Altera_Forum]

dwh -- That's puzzling, b/c QSYS gives the following error message 

"Signal master[8] and signal avalon_slave_0[16] must have the same symbol width"  I guess I could make the system 32-bit, but I'd prefer to figure out what's going on here. I thought that the bus width was automatically handled under QSYS.  I'm just using QSYS to connect the bus fabric and for the JTAG debug capability. The FPGA attaches externally to a separate DSP.

[Altera_Forum]

--- Quote Start ---   That's puzzling, b/c QSYS gives the following error message "Signal master[8] and signal avalon_slave_0[16] must have the same symbol width"   --- Quote End ---  That sounds like a how many bits per byte issue. Look in the _hw.tcl file for your component and see if you have a 16-bit symbol size, rather than 8-bit symbol size.    --- Quote Start ---   I guess I could make the system 32-bit, but I'd prefer to figure out what's going on here. I thought that the bus width was automatically handled under QSYS.  I'm just using QSYS to connect the bus fabric and for the JTAG debug capability. The FPGA attaches externally to a separate DSP.  --- Quote End ---  The JTAG-to-Avalon-MM master, and SignaTap II are very useful for debugging problems, so its definitely worth figuring out what is wrong.  Cheers, Dave

[Altera_Forum]

Dave -- Thanks. It was a symbol width mismatch. I had not understood why Altera was asking for the symbol size and had defined the 16-bit bus width parts as having 16-bits per symbol. Now I also understand the addressing increments as well. This is great.

[Altera_Forum]

--- Quote Start ---  It was a symbol width mismatch. I had not understood why Altera was asking for the symbol size and had defined the 16-bit bus width parts as having 16-bits per symbol. Now I also understand the addressing increments as well.  --- Quote End ---    Great! Now you can move onto your next problem :)  Cheers, Dave