Ref Clock Pin 10G ATX PLL

Altera_Forum · ‎03-24-2010

Hi,

In the Stratix IV Device Handbook Volume 2, page 1-197 they say:

"For the 10G ATX PLL, Stratix IV GT devices only allow driving the reference clock

source from one of the dedicated reflck pins on the same side of the device.

For improved jitter performance, Altera strongly recommends using the REFCLK pins

of the transceiver block located immediately below the 10G ATX PLL block to drive

the input reference clock."

Does anyone know, which pin they actually mean?

We are planing to use the EP4S100G5F45I2 FPGA (1932 Pins)

Cheers

Altera_Forum · ‎03-30-2010

Solution/Workarround:

Since the 10G ATX PLL can only drive 4 GXB channels (according to the Stratix IV GT Errata list), the CMU0 PLL of each GXB block is used to generate the clock and for this PLL there are dedicated REFCLK ports for each of these PLLs.