Register and/or PLL reset when loading Arria II GX via JTAG?

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Register and/or PLL reset when loading Arria II GX via JTAG?

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How do i create a valid system reset when loading the FPGA via JTAG? I have found that PLLs are not reset except on power-down of the whole chip. The pll.locked output stays high during and after configuration via JTAG.

Thanks.

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