Remote update Flash EPROM (EPCS16) using lan/ uart

[Altera_Forum]

Hello all, 

 i have question. I need to update throw ethernet my flash memory EPCS16 on some board with EP3C16 FPGA. The ethernet i convert to uart using xport and the data from uart i need to save to the flash eprom. Is some finished application (bitstream and sw.), how to convert uart stream of bytes to the flash EPCS16 ? I need a lot of answers, but something like this i didnt find. I found that in HAL i can use the commands for read and write to/from flash, but i think, that it is solved....   Thank you for your answer.  Jan Naceradsky

[Altera_Forum]

Hi Jan: 

 First a question:  Is the ethernet controlled through the FPGA, or do you have a cpu with Ethernet on the board? The main concern here, is I want to know where the image is store in after it comes off the ethernet.  There are a few ways this can be accomplished:  One is through a uart slave core in the fpga that talks to ALTREMOTE_UPDATE megafuncton in the FPGA to write, verify and boot a secondary image in the EPCS.  We have done it that way with success, but we wrote our own custom uart interface, with slip streaming, and addressing scheme to make it work. This is the best way, if you only have a uart interface, and no direct micro or cpu on the board.  The second way is to wire up the EPCS directly to both the CPU and FPGA, so the FPGA can boot from this in active serial mode, then the CPU can take control and access the EPCS directly. This is a little more risky, in that at boot up, you must insure the FPGA can read from the EPCS as it expects. We have done this when we had a small micro on the design that didn't have it's own external flash memory to store the bitfile. I don't really like this method however.  A third way, if your CPU doesn't require the FPGA as part of it's boot process, is to have the CPU program the FPGA at each boot up in passive serial mode. This way the image is stored in the CPU's flash memory. We tend to use this most often if there is a master CPU in the design outside of the FPGA.  I work for INFINETIX, an engineering consultant group. If you are working for a company with specific needs we can help you out. www.infinetix.com.   If you are a student, working on a project, keep asking specific questions as you go along and get stuck, people on the forums are pretty good.   Pete

[Altera_Forum]

Hi Pete, 

 thank you for your answer.  I dont control ethernet through FPGA or cpu, I use the Xport  http://www.lantronix.com/device-networking/embedded-device-servers/xport.html  which can convert uart <-> ethernet and FPGA control (read/write) the uart.  The second and third way we used in last time and it work but it seems complicated.  The first way could be the best way. But i must study ALTREMOTE_UPDATE megafunction, how it works.  Jan

[Altera_Forum]

Hi Jan: 

 Yes, I've very familiar with the Lantronix devices. We did several designs with the Xport-AR several years ago. And are currently supporting them and some successors with newer Xport devices.  I agree with this setup the UART interface would be the best.  http://www.altera.com/literature/ug/ug_altremote.pdf is the userguide for the megafunction.  One issue we ran into is the simulation model of the megafunction is non-existant, so we did use signal tap to make sure it was working correctly.  In our design the UART communications and register interface to talk to the megafunction was all custom logic.. We did slip streaming with parity and CRC error detection, to make sure it was programmed with valid data.  The use case for this, is you still need to initially program the EPCS with a initial bitfile that has the REMOTE_UPGRADE megafuction. But this allows you to write a secondary image and switch over to that secondary image with a fall back to the initial image if it failes.  It works well, and the fall back is nice. Basically we had the master system do a version check on the bitfile, if it didn't match what was expected it would try the secondary bit file and check versions again. If it fell back to the first bitfile, or the version still did not match, it would program the new bitfile into the secondary space, and try the switchover again.  Pete

[Altera_Forum]

Hi, 

 i am back to solve remote update and i have question - how can i start to reconfigure fpga ? In remote_upgrade megafunction is described some registers, but the exact way how to start reconfiguration without external pin nConfig or nStatus i didnt find. Is some way how to reconfigurate fpga without remote_upgrade megafunction and without external pins ?   Thank you for answer.  Jan

[Altera_Forum]

--- Quote Start ---  Is some way how to reconfigurate fpga without remote_upgrade megafunction and without external pins ?   --- Quote End ---   Why don't you want to use the remote_upgrade megafunction? What you need is a minimal interface to the remote upgrade megafunction, needing just a single register of your application and the rem_update block existing in the FPGA hardware.  rem_update_inst : rem_update PORT MAP ( clock => CLK, reset => RESET, reconfig => reconfig_req );

[Altera_Forum]

I can use remote_upgrade megafunction, but in datasheet i didnt find how to reset fpga and start update inside fpga ...

[Altera_Forum]

The reconfig does what the signal name says, start a reconfiguration.  

 Without setting additional registers in the remote_upgrade block, the effect is similar to asserting NCONFIG.   Just try...

[Altera_Forum]

It is not so simple how you write or i have some error on my design or program. I have design, where i have altremote_update0 megafunction connect to NIOS2/f to LED_BASE led[15] to reconfig pin and led[14] to reset pin and i have this part of program: 

-----------------------------------  printf("Restart altremote_update.\n");  IOWR_ALTERA_AVALON_PIO_DATA(LED_BASE,0x4000);  usleep(10000);  IOWR_ALTERA_AVALON_PIO_DATA(LED_BASE,0x0);  // open flash  printf("Oteviram flash EPROM.\n");  fd = alt_flash_open_dev("/dev/epcs_flash_controller_0");  if (fd!=NULL)  {  printf("Info flash EPROM.\n");  ret_code = alt_get_flash_info(fd, &regions, &number_of_regions);   if (!ret_code)  {  printf("Flash EPROM obsahuje %d sektoru.\n", regions->number_of_blocks);  for(n=0;n<regions->number_of_blocks;n++)  { printf("Erase %d.sector.\n",n);  if (fd!=NULL) alt_erase_flash_block(fd, n*65536, 65536);  }  printf("Wait on data in UART.\n");  }  }  init_uarts();   // main cycle  while (1)  {  // write uarts data to flash eprom  if (rx_lan_flag1==1)  { alt_printf("%x ",blok_cnt);  // reverzuj bity  ReverseBitsInBytes(data_written, 256);  // write block  if (fd!=NULL) ret_code = alt_write_flash_block(fd, 0, blok_cnt*256, data_written, 256);  rx_lan1=0;  rx_lan_flag1=0;  blok_cnt++;  }   // read data  if (blok_cnt==16*256)  { printf("Reading flash EPROM.\n");  for(m=0;m<blok_cnt;m++)  { ret_code = alt_read_flash(fd, m*256, data_read, 256);  // reverzuj bity  ReverseBitsInBytes(data_read, 256);  // list only 16 bytes from 256-bytes block  printf("%04X:",m);  for(n=0;n<16;n++)  { printf("%02X",data_read[n]);  }  printf("\n");  }  printf("Close flash EPROM.\n");  alt_flash_close_dev(fd);  blok_cnt=0;  printf("Perform reconfiguration - write 1 to config.pin.\n");  IOWR_ALTERA_AVALON_PIO_DATA(LED_BASE,0x8000);  usleep(10000);  IOWR_ALTERA_AVALON_PIO_DATA(LED_BASE,0x0);  } ------------------------------ Everything is ok, but reconfiguration does not start after  IOWR_ALTERA_AVALON_PIO_DATA(LED_BASE,0x8000); usleep(10000); IOWR_ALTERA_AVALON_PIO_DATA(LED_BASE,0x0);  When i turn off and turn on power supply of the board, it takes the bitstream which i programed to flash and it work well.  Is possible to set some registers on altremote megafunction or something else ? Clock for NIOS is 120MHz and for altremote megafunction 20MHz. In NIOS is not any timer ...  Thank you for your answer.  Jan

[Altera_Forum]

No idea why the configuration request isn't working. 

 You should check in the technology mapper view how the reconfic signal is actually connected.  You also must select Configuration Mode = Remote under Assignments/Device/Device and Pin Options/Configuration/ (set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE).

[Altera_Forum]

Yes, i select Configuration Mode = Remote, i use 10MHz clock for altremote megafunction, the last what i find, that we have nConfig external connect to with pull-up 10k to VCC 3,3V. 

We use EP3C25E144.

[Altera_Forum]

I have some questions yet: 

1) How can i guarantee that reconfig from nios takes 500ns and more, when i set reconfig to "1" and it should cause restart all fpga chip (in next clock edge) ? 2) These other pins dont need to connect to some vcc or gnd ? (design.png) 3) And in Technology Map Viewer the design of altremote megafunction hasnt connected pin reconfig ? ...  Is somewhere simple design with nios, epcs and sltremote megafunction for cyclone III ?  Thank you for answer.

[Altera_Forum]

I am sorry, it was my and Quartus error. When i erase and include the altremote megafunction and connect to nios2 through another port (enable_bus), it works OK. 

 Jan

[Altera_Forum]

--- Quote Start ---  I am sorry, it was my and Quartus error. When i erase and include the altremote megafunction and connect to nios2 through another port (enable_bus), it works OK.  --- Quote End ---   Yes, you can see that the !RCONFIG input is unused (connected to 1) in the netlist of your previous post.  Good that it works.

[Altera_Forum]

Yes, now, when i start from 0x0 address it works. 

But i have new question. I possible to start reconfig from flash eprom from 0x00|10|00|00 = 1MB ? How ? I have code, which write to the flash from 1MB over (0x00100000-0x001FFFFF) and after this i try to start from address 1MB: -----------------------------------------------------------------------------  printf("Set boot address 0x100000.\n");  // i must shift the address 0x00100000 to the right 2 bits  IOWR_ALTERA_AVALON_PIO_DATA(ENABLE_BUS_BASE,0x00040000);  usleep(1000);  printf("Write the boot address 0x100000.\n");  // address + param + write  IOWR_ALTERA_AVALON_PIO_DATA(ENABLE_BUS_BASE,0x00040000|0x01000000|0x02000000);  usleep(1000);  printf("Start reconfiguration.\n");  IOWR_ALTERA_AVALON_PIO_DATA(ENABLE_BUS_BASE,0x80000000); ------------------------------------------------------------------------- but it start again from 0x0.  Where could be error ?  Or is there only one possibility and it is to start from 0x0 ? (in altremote_ug or an521 it looks, that it could be able, but exact description, how to make it, i didnt find.)  Thank you for your answer.  Jan  In attachment i include the connected altremote_megafunction.

[Altera_Forum]

For an Nios based RSU example, you can also refer to Altera Wiki http://www.alterawiki.com/wiki/epcs_based_remote_system_update_(rsu)_example_on_bemicro_sdk 

 I don't use remote system upgrade with NIOS, but at first sight you are setting the boot address right. Other parameters must be set, too. The watchdog must be e.g. explicitely disabled.

[Altera_Forum]

I didnt find, how to disable watchdog for Cyclone III (i have EP3C25) in altremote_update megafunction user guide. 

The example should be fine, but i am not familiar with linux and script file, so my compilation in Quartus 12.0 finished with error: Error (12006): Node instance "id_tcm_app_ram_32k" instantiates undefined entity "test_sys_top_qsys_id_tcm_app_ram_32k"  So, how to disable watchdog or how to start reconfiguration from another address than 0x0 ?  If it is not possible i can copy factory image 0x000000-0x100000 to second half of flash, then read bitstream from uart and download its to low half of flash ... and after this start reconfig.

[Altera_Forum]

--- Quote Start ---  So, how to disable watchdog or how to start reconfiguration from another address than 0x0 ?  --- Quote End ---   For the parameters of altremote_update MF available for Cyclone III, please refer to table 8 of the most recent remote update ip core user guide. You should at least disable the Watchdog (provided it's not served in your application) and set the boot address (as you already do). The examples set also the osc_int and cd_early bit options, althoug it's probably not required. I didn't check, just performed the suggested actions.    --- Quote Start ---  If it is not possible i can copy factory image 0x000000-0x100000 to second half of flash, then read bitstream from uart and download its to low half of flash ... and after this start reconfig.  --- Quote End ---   That's surely possible but not intended usage of remote system upgrade. If the action fails somehow, you end up with non-functional system and need to connect a JTAG programmer. The idea is to keep the factory image as safe fallback option.

[Altera_Forum]

Thanks, i again download last user guide, but it is same, which i have had ... www.altera.com/literature/ug/ug_altremote.pdf. 

 Table 8 is located from page 19 - 22, but which bit disable watchdog (in attachment).... ? I dont see this, so nothing, i appear AN603 www.altera.com/literature/an/an603.pdf  and now i can study all from this :) So i thing, that Altera hasn´t well described this megafunction and the example for nios would be useful for many people...

[Altera_Forum]

--- Quote Start ---  but which bit disable watchdog  --- Quote End ---   The table tells that parameter 100 must be written to 0. AN603 documentation has even signal tap waveform of individual parameter read and write operations, but the parameter addresses are for Arria II.  Generally, you can do some debugging to find out what happens in your previously described test. You try to start the application image and it fails. But waht happens: - no reconfig started at all - reconfig with wrong start address - reconfig with right address but invalid image - reconfig with valid image but watchdog causes reboot

[Altera_Forum]

Thank you for your support. I have more errors in this project. The first it was wrong address - shift to the left not to the right - bad address=0x00400000, correct address=0x00040000 (i had have only one 0 more:)), bad number code for disable watchdog and when i erase and program the flash eprom it was neccessary to close flash eprom. 

I first try it on board DE0 Nano, so i include my project, when is possible to switch two bitstreams (one start on 0x0 address and second start on 0x00100000). After this i copy to my board and now it works.:)  Jan Naceradsky, Czech Republic