Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Reverse Engineering a classic CPLD

Altera_Forum
Honored Contributor II
‎07-17-2014 12:00 PM
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I have been tasked with reverse engineering an ancient PCB that has a EP610 and EP220 on board. I have the .jed files which verify with the devices. My question is, does anyone know how the .jed file refers to the "fuse" matrix within the CPLDs so that I can figure out what the logic is actually doing rather than what I think it is doing and so put it in an available device? 

 

Many thanks 

 

Neil
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Altera_Forum
Honored Contributor II
‎07-21-2014 04:41 PM
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Hi There! 

 

I have no idea but it's an interesting question :-) Rather than trying to reverse engineer the fuse pattern, wouldn't it be easier to just emulate the behavior? That is, if the device still works. Depending on the complexity, you should be able to observer its behavior on a logic analyzer, no? 

 

-Mux
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