SOPC based PCIe design issue

[Altera_Forum]

Hi 

 I was building an SOPC based design with PCIe as a component. I instantiated the design and enabled the required clocks. After downloading the design, when i restart the computer, the computer switches OFF before starting again. I am using a DE4 board for the design. The PCIe demo provided by Terasic works fine. Any pointers as to any signals i might be missing.   The following are the signals that i have instantiated particular to pcie.   .cal_blk_clk_0(enet_refclk_50MHz),  .busy_altgxb_reconfig_pcie_compiler_0 (busy),  .fixedclk_serdes_pcie_compiler_0 (enet_refclk_125MHz),  .gxb_powerdown_pcie_compiler_0({~PCIE_PREST_n}),  .pcie_rstn_pcie_compiler_0(PCIE_PREST_n),  .pll_powerdown_pcie_compiler_0({~PCIE_PREST_n}),  .reconfig_fromgxb_pcie_compiler_0(reconfig_fromgxb),  .reconfig_togxb_pcie_compiler_0(reconfig_togxb),  .refclk_pcie_compiler_0(PCIE_REFCLK_p),  .rx_in0_pcie_compiler_0(PCIE_RX_p),   .test_in_pcie_compiler_0(test_in),  .test_out_pcie_compiler_0(test_out),  .tx_out0_pcie_compiler_0(PCIE_TX_p),  .reconfig_clk_pcie_compiler_0(enet_refclk_50MHz),  I have instantiated a altgx_reconfig core with offset_cancellation_reset input for generating the busy signal. The signal tap shows all the clocks running properly. Any idea as to why the issue might be happening.  Thanks & Regards Hari

[Altera_Forum]

Can anyone suggest how to successfully get the PCIE design to work in an SOPC builder system. I am using DE4 board. I seem to be missing some connection, which i am not able to figure out. 

 Regards Hari

[Altera_Forum]

Hari, 

 I'm using DE4 board. Which generation of PCIe are you using? Gen1/2? Also how many lanes? Which clock are you using from DE4? As for your instantiation goes, it looks correct. I'm working on Gen1 x4, but it always down trained to x1 lane. If you were able to make x1, but not x4, we are on same boat.

[Altera_Forum]

Hi Kattice, 

 In SOPC builder i was using Gen2 version. It allows only x1 data lane. I am able to get it working in Gen 2 x8 when using the Avalon ST version. Only when trying in the SOPC builder it is not working properly. If you have got it working in the SOPC builder can you share the details of the design.    Thanks & Regards Hari

[Altera_Forum]

What's your PCIe interface goal? Gen1/2? x1,x4, or x8? Gen1 and Gen2 requires different clock. Gen1 requires 125M and Gen1 can take 100M or 125M according pice user guide from Altera.  

 I'm using Gen1 only. It sounds like we may be in same boat. Depending on compilation, I get x1 trained up link or x4 trained up link. I'm looking into SDC constraints for PCIe interface. What's your SDC constraint?

[Altera_Forum]

As far as I know SOPC won't support Gen2. It only supports gen1. 

Qsys can support up to gen2x4. ST interfaced one is totally different. You may have to have TLP decoder in order to use it with/in SOPC.

[Altera_Forum]

Hi Kattice 

 I am trying to use a custom component to connect to the MM side of pcie. I can use either Gen 1 or Gen 2, just need to get it working in SOPC. But i am facing the issue i mentioned. I tried ST version to make sure pcie is working fine. I am using the 100 Mhz clock and generating the 50Mhz(reconfig_clk) and 125Mhz(fixed_clk) using a PLL. Also the inverse locked output from the pll is used as offset_cancellation_reset for altgx_reconfig .  Hi nekojiru,  In SOPC builder I am able to select the Gen2 version. Do you mean it will still not work. I will try with the Gen1 version and see whether i can get the pcie to work  Thanks a lot for the reply.  Regards Hari

[Altera_Forum]

Sorry, it seems like gen2x1 is available after the new release of Quartus.

[Altera_Forum]

May I know which PC you are using? 

Also, is it possible for you to try on other PC?  The code looks ok for me...

[Altera_Forum]

Hi nekojiru, 

 I am using HP xw 4600 Work station. Is there anything else that need to be connected other than the SOPC instance. For the ST version basically i use the chaning dma app that is auto generated. Is some other component required for the case of SOPC builder for the pcie to initialize.   Regards Hari

[Altera_Forum]

As far as i recall, there should be other requirements, though I only did it in the Q10.1, so it may have changed. 

I assume you've set reconfig_fromgxb and reconfig_togxb to be the right width. If you are enabling the PIPE interface, then you need to assign right input for them as well.  If you are saying DMA is not working fine or the performance is low, then lot of places to look at, but PC does not boot, sounds like fundamental. You might want to check the pin assignment, just in case. Also, the clk setting.  If the Terasic design is working with gen2x1, you might want to compare the pin and clk settings.

[Altera_Forum]

Harikris, 

 Your clock setup is okay. Stay with Gen1 for now. I recommend using x1 to start with. Which clock are you using from DE4 board? I'm using "gclkin" (100MHz) from schematic page 6. Use this as your free running clock. Make sure you set SW7 switch for 100MHz. Use this clock to generate 50MHz and 125MHz for your system. I hope this helps.

[Altera_Forum]

Hi Kattice, 

 Could please tell about the altgx_reconfig instance that you used. Which all signals did you enable for this instance.  Regards Hari

[Altera_Forum]

Hi Kattice & nekojiru, 

 I got the issue solved. It was due to the PCIe(x16) slot itself. I changed to another x8 slot and my designs are working fine. Never tried to check this before since PCIe Fundamental demo was working fine.   Thanks & Regards Hari

[Altera_Forum]

Glad to hear that it's working. Are you using x4 or x8? I noticed also that CPU or chipset do make difference how they are trained up. I'm having issue with IP timing issues when I use x8 lane. Do you have timing issues?

[Altera_Forum]

I used both Gen1 and Gen2 x1 configurations. I am using the MM signals to just write to some registers for now. Did not get any timing issues. I will try x4 or x8 and reply back. 

 Regards Hari