Single Rank DDR3 setup

Altera_Forum · ‎08-01-2014

Hi All,

Our product has two Micron MT41J64M16LA-15E DDR3 chips. Both have their own discrete PCB traces to each pin (the point is the two DDRs are mutually exclusive). What I want to do is use them as one single Rank, where I can write 32 bits to the pair (16 lower to one, 16 high to the other). Can anyone point me to a diagram and or some code that shows the proper way to do this?

My first swag at this was to change the parameters such that the DQ bus was 32 bits wide, and make two clocks. Then I hooked them up like this at the top level of my code.

This is the MC ports from the component declaration:

mem_clk : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0);

mem_clk_n : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0);

mem_reset_n : OUT STD_LOGIC;

mem_dq : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);

mem_dqs : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);

mem_dqsn : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);

mem_odt : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);

mem_cs_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);

mem_cke : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);

mem_addr : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);

mem_ba : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);

mem_ras_n : OUT STD_LOGIC;

mem_cas_n : OUT STD_LOGIC;

mem_we_n : OUT STD_LOGIC;

mem_dm : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);

mem_addr_13 : OUT STD_LOGIC

From my MC instance, here are the ports out.

mem_clk => mem1_clk,

mem_clk_n => mem1_clk_n,

mem_reset_n => mem_reset_n,

mem_dq => mem1_dq,

mem_dqs => mem1_dqs,

mem_dqsn => mem1_dqsn,

mem_odt => mem_odt,

mem_cs_n => mem_cs_n,

mem_cke => mem_cke,

mem_addr => mem_addr,

mem_ba => mem_ba,

mem_ras_n => mem_ras_n,

mem_cas_n => mem_cas_n,

mem_we_n => mem_we_n,

mem_dm => mem1_dm,

mem_addr_13 => mem_addr_13

Then I assign the memory controller to the top level ports as such:

mem1_clk <= mem_clk(0 downto 0);

mem1_clk_n <= mem_clk_n(0 downto 0);

mem1_reset_n <= mem_reset_n;

mem1_dq <= mem_dq(15 downto 0);

mem1_dqs <= mem_dqs(1 downto 0);

mem1_dqsn <= mem_dqsn(1 downto 0);

mem1_odt <= mem_odt;

mem1_cs_n <= mem_cs_n;

mem1_cke <= mem_cke;

mem1_addr <= mem_addr;

mem1_ba <= mem_ba;

mem1_ras_n <= mem_ras_n;

mem1_cas_n <= mem_cas_n;

mem1_we_n <= mem_we_n;

mem1_dm <= mem_dm(1 downto 0);

mem1_addr_13 <= mem_addr_13;

mem2_clk <= mem_clk(1 downto 1);

mem2_clk_n <= mem_clk_n(1 downto 1);

mem2_reset_n <= mem_reset_n;

mem2_dq <= mem_dq(31 downto 16);

mem2_dqs <= mem_dqs(3 downto 2);

mem2_dqsn <= mem_dqsn(3 downto 2);

mem2_odt <= mem_odt;

mem2_cs_n <= mem_cs_n;

mem2_cke <= mem_cke;

mem2_addr <= mem_addr;

mem2_ba <= mem_ba;

mem2_ras_n <= mem_ras_n;

mem2_cas_n <= mem_cas_n;

mem2_we_n <= mem_we_n;

mem2_dm <= mem_dm(3 downto 2);

mem2_addr_13 <= mem_addr_13;

And this is the error Im getting:

Error (17044): Illegal connection found on I/O input buffer primitive Video_Memory:

Inst_Video_Memory_1|ddr3_controller:Inst_DDR3_Controller|ddr3_controller_controller_phy:ddr3_controller_controller_phy_inst|ddr3_controller_phy:

ddr3_controller_phy_inst|ddr3_controller_phy_alt_mem_phy:ddr3_controller_phy_alt_mem_phy_inst|ddr3_controller_phy_alt_mem_phy_dp_io:

dpio|dqs_group[0].ddr2_with_dqsn_buf_gen.dqs_inpt_ibuf. Source IO Video_Memory:

Inst_Video_Memory_1|ddr3_controller:Inst_DDR3_Controller|ddr3_controller_controller_phy:ddr3_controller_controller_phy_inst|ddr3_controller_phy:

ddr3_controller_phy_inst|ddr3_controller_phy_alt_mem_phy:ddr3_controller_phy_alt_mem_phy_inst|ddr3_controller_phy_alt_mem_phy_dp_io:

dpio|dqs_group[0].ddr2_with_dqsn_buf_gen.dqs_obuf also drives out to other destination than the buffer.

Anyone have any ideas why this is? BTW this is an Arria II GX, on Quartus 13.0.1 build 232. I should be able to reassign signals, correct? The error above on Alteras site says I have a fanout of more than one, but that is not true, the DQS and DQ pins are all exclusive.

http://quartushelp.altera.com/11.1/mergedprojects/msgs/msgs/escl_scl_illegal_wys_io_ibuf.htm

Thanks in advance for any help!