Due to powersave requirements, my board has the ability to switch the FPGA / DDR memory / sensor part off, if not used for a certain time. I consider this similar to a hot-socketing behaviour, which is supported by Stratix III devices.
I'm now facing the problem, that the FPGA pwrreset_n input (on-board POR going to FPGA, STM32 and FX2 devices) is tied low by the FPGA IO during a short time when ramping the power rails up, causing the other devices (FX2 / STM32) to reset, which is unwanted.
According to manuals "...the Stratix III device does not drive out until the device is configured..." so I'm a little confused about that.
Further fact: Only boards assembled with EP3SL70 show the behaviour, EP3SL50 don't tie low the mentionned IO in an otherwise unchanged environment.
I attached two CRT shots showing my power sequence, currently using ratiometric tracking of 2V5 for 1V8 and 1V1VCCL. Coincident tracking of the same rails showed the same behaviour. To my understanding, the powerup sequence is within the recommended behavior concerning rise time and monoty.
Any idea why this IO drives low at this time where it shouldn't?
