Stratix V CONF_DONE but no INIT_DONE

[Altera_Forum]

Hi everybody, 

 We have a 5SGSED6N3F45 on a custom board that we're trying to configure over JTAG. We can't get the device to finish initialization and enter user mode. The CONF_DONE signal is asserted then released less than a second later, while the Quartus II programmer continues to program through our on-board USB Blaster II for 15 to 20 seconds. The INIT_DONE signal is never released and none of the output buffers are ever enabled.  The INIT_DONE pin is enabled in the design and pulled up on the board. The device is set to use the internal clock for initialization.   What can cause a Stratix V to fail during initialization?  Thanks, Danny

[Altera_Forum]

Can you confirm that your USB-Blaster II works correctly, eg., by reading the JTAG IDCODE or performing some other JTAG sequence like BYPASS? 

 How did you obtain access to the USB-Blaster II design? Did you license it from Altera or reverse-engineer it? I'm interested in learning about the design, but have not found any published details.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Can you confirm that your USB-Blaster II works correctly, eg., by reading the JTAG IDCODE or performing some other JTAG sequence like BYPASS?  --- Quote End ---   I can confirm that the USB Blaster works. It detects the device just fine and it was used to program another CPLD on the board with no issues. It also reports success upon completion -- if I pull nCE high, the programmer (via the USB Blaster) reports failure at 97%

[Altera_Forum]

--- Quote Start ---  I can confirm that the USB Blaster works. It detects the device just fine and it was used to program another CPLD on the board with no issues.   --- Quote End ---   Ok.    --- Quote Start ---   It also reports success upon completion -- if I pull nCE high, the programmer (via the USB Blaster) reports failure at 97%   --- Quote End ---   Sorry, its not clear what you mean here ... completion of the CPLD, or completion of the FPGA?  Do you have a development board with the same FPGA on it and a USB-Blaster II interface? You could create a design with something as simple as a JTAG-to-Avalon-MM bridge and some internal registers/ram, so that it has no I/O. You could then download that to your known-good development board to confirm that the image is good. If you then download that same image to your custom board and it does not work, you then know that the problem is related to your hardware (rather than some issue with FPGA image generation).  Random thought; I recall some issues with security modes on engineering samples (but do not recall if the issue was Stratix V related). Check the errata for your device and see if there is anything weird you have missed that might be related to this problem.  Cheers, Dave

[Altera_Forum]

It turns out that we had CVP enabled in the device settings. Disabling CVP altogether allowed the device to configure and initialize properly from both the on-board USB blaster II and an off-board USB blaster pod.

[Altera_Forum]

--- Quote Start ---  It turns out that we had CVP enabled in the device settings. Disabling CVP altogether allowed the device to configure and initialize properly from both the on-board USB blaster II and an off-board USB blaster pod.  --- Quote End ---   Excellent! Glad to hear you resolved your issue.  I'm still interested in learning about your USB-Blaster II design. Feel free to email me at my forum name if you'd prefer not to comment on a public forum.  Cheers, Dave