We have a 5SGSED6N3F45C4N on a custom board connected to a Cypress CY7C2663KV18 QDR-II+ memory. We're providing a 100 MHz 1.5V DHSTL reference clock FPGA device pins BC8 and BD8 (the CLK11 pair) and trying to run the QDR-II+ memory interface at 200 MHz. Unfortunately, the PLL in the QDR controller won't lock. Using SignalTap, we observe the PLL lock indicator bouncing around, and using an oscilloscope on the output clock pins, we see the clock idle (railed high), operating at 200 MHz occasionally, and more often operating at 400 MHz.
What can cause the PLL in the Stratix V QDR-II+ controller to be unable to lock?
