What is the difference between direct arithmetic computation and using MegaWizard blo

[Altera_Forum]

When I try to do addition, reduction, multiplication, previously I will use  

plug ins in Quartus II like LPM_ADD_SUB. Then I will program use this addtion block to do addtion.The program will be:  module Test1121(out1,out2,a,b); input [7:0] a,b; output [8:0] out1; output [15:0] out2;  add1(a,b,out1); mul1(a,b,out2);  endmodule   However, It seems I can directly programing like this:  module Test1121(out1,out2,a,b); input [7:0] a,b; output [8:0] out1; output [15:0] out2;  always@(a or b) begin out1=a+b; out2=a*b; end endmodule   So I wonder what is the difference between them? Which one is better to be used? Thanks

[Altera_Forum]

writing HDL is obviously more portable between FPGA vendors, ASICs, and doesn't require Altera specific simulation libraries 

 i have seen better fmax numbers using LPM functions rather than HDL - i think the LPMs are implemented at an atom level rather than being synthesized, so they are or can be pretty well optimized

[Altera_Forum]

in theory you should be able to get HDL to be pipelined just like the LPM but it will probably not be as simple as: 

 out2=a*b;

[Altera_Forum]

Pipelinening (with more than an input and output register) can be easier specified with MegaFunctions. Unregistered arithmetic, as shown in this post should give identical results, because arithmetic inferred from HDL uses the same lpm_add and lpm_mul blocks, as you can see from the RTL netlist. Of course there may be cases, where the implementation looks slightly different.

[Altera_Forum]

That means for better performance, I should use the LPM_ADD_SUB,right?

[Altera_Forum]

U means they are actually same?

[Altera_Forum]

FvM makes a good point about the pipelining

[Altera_Forum]

--- Quote Start ---  U means they are actually same?  --- Quote End ---   Yes. "Direct" arithmetic in behavioral HDL code is the preferred way for daily FPGA coding. Only division suggests structural (MegaFunction based) code because divider inference is rather limited.

[Altera_Forum]

Thanks very much. But why I ask this one in Altera Mysupport, I got the following answer, which causes me confused again: 

 I answer your question as below.  The Altera® integer arithmetic MegaWizard offer user the convenience of performing mathematical operations on FPGAs through parameterizable functions that are optimized for Altera device architectures.   These functions offer efficient logic synthesis and device implementation.  User can customize the megafunctions by configuring various parameters to accommodate the needs.  Altera always recommend user using the MegaWizard in order to have the optimized synthesis result.

[Altera_Forum]

FvM: in addition to division, i would recommend doing multiplication with widths greater than signed 18x18 with an LPM_MULT. writing optimized HDL for wide multiplies can be tedious

[Altera_Forum]

Or put it more generally, which is better inference or instantiation. 

from code readability point of view we all like inference and specially so young designers as the compact code looks more impressive. At the other extreme, some poor beginners instantiate registers, or even constants, ...etc.  I always infer registers and will never instantiate them even if I fail the exam??, I always infer isolated adders/subtractors/counters etc. And certainly constants, I don't know why vendors don't remove these dead legacy components completely from their libraries. I used to infer multipliers but not anymore for good reasons. I avoid dividers whenever possible by using inverse multiplication. For dedicated blocks Vendors produce richer features for their components than inference which may support fully, partially or never. The idea of inference is supposed to be just another way to call the same component from library(usually). As to portability across vendors, this is practical for small designs as normally you will end up with some instantiations especially so for memories. I think it is better to redesign and have more time to be paid...this is far more important for your portability yourself.

[Altera_Forum]

insightful, kaz

[Altera_Forum]

Despite that neither me nor cris72 managed to get decorated as FvM, 

Cris is still well at the lower end...after his initial excitement !!!

[Altera_Forum]

not sure why that is 

 i'm not normally good about clicking that button, i'll see if i can pay attention a bit better