When to use virtual clock

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

When to use virtual clock

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Hi.

I have read a lot of articles mention that virtual clock is used when the data drive off or enter the chip.

However, i have a lot of examples that they do not use the virtual clock in set_input_delay and set_output delay or use either one of the sdc commands.

How to justify it?

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