Why can't I generate a PCIe example design？

[allen18]

[wchiah]

Hi,

Can I know which version of quartus you are using ?

Normally this error happen when

When you clean project, the folder of IP in your case XXX.ip is being deleted.

Therefore, you have to re-generate HDL of XXX.ip before you can generate HDL of your qsys system.

Then add_fileset_file "file not found" error should be resolved.

Regards,

Wincent_Intel

[wchiah]

Hi,

You should click the "Reply" before you can post the "Post Reply"

Can you please provide me the device OPN ? I will try to replicate this on my place and see if I can see the same error as yours or not.

Regards,

Wincent_Intel

[wchiah]

Hi,

Can I get your agreement to close this loop as replicate ?

we shall move our conversation to https://community.intel.com/t5/forums/forumtopicpage/board-id/programmable-devices/message-id/92371#M92371

For better tracking purpose, do you agree ? Let me know if you have different thoughts.

Regards,

Wincent_Intel