a strange problem!

[Altera_Forum]

module zhengxing(clk_200M, 

rst, data_in, data_out ); input clk_200M; input rst; input data_in; output data_out; reg data_out; reg [2:0]counter;  reg [1:0]state; parameter low=2'b00, wait_high=2'b01, high=2'b10, wait_low=2'b11;   always @ (posedge clk_200M or posedge rst) if(rst==1) begin counter<=0; data_out<=0; state<=low; end else case(state) low:if(counter>=3) begin data_out<=0; state<=wait_high; end else begin counter<=counter+1; // data_out<=1; state<=low; end wait_high:if(data_in==1)  begin state<=high; counter<=0; ///data_out<=0; end else begin state<=wait_high; counter<=0; //data_out<=0; end high:if(counter>=3) begin data_out<=1; state<=wait_low; end else begin state<=high; counter<=counter+1; end wait_low:if(data_in==0) begin state<=low; counter<=0; end else begin state<=wait_low; counter<=0; end default:state<=low; endcase endmodule    there is no error in it.and the simulation is also right ,but when it is in the fpga ,it doesn't work.and the out port is always high ; i don't know it's why! who can help me? thank you!

[Altera_Forum]

I assume clk_200M is a 200 MHz clock signal. Perhaps this is too fast for the FPGA you are using. Which FPGA and speed grade are you using?

[Altera_Forum]

As a start, for debug purposes, remove or comment out all the logic in the process and just tie your outport to 'low' to see if this pin can toggle. 

 ie. data_out <- '0'. Observe this at the FPGA out and if this pin is still staying high then check your drive strengths for that pin in your qsf file.

[Altera_Forum]

i change the clk from 200M to 20M,but it also didn't work; my fpga is ep2c5t144c8

[Altera_Forum]

this io is well !and i connect the input pin to output pin 'data_out' ,the wave is the same as the input pin, so i don't think the pin has problem!

[Altera_Forum]

--- Quote Start ---  this io is well !and i connect the input pin to output pin 'data_out' ,the wave is the same as the input pin, so i don't think the pin has problem!  --- Quote End ---     Hi,  I assume that the code represents the whole design ??? If yes, please post your project in the forum.  Kind regards  Gerd

[Altera_Forum]

--- Quote Start ---  Hi,   I assume that the code represents the whole design ??? If yes, please post your project in the forum.   Kind regards   Gerd  --- Quote End ---       this module is only use to do with square wave,when the square wave with some unstable signal on its edge input into the input pin ,i want to use this module to get a stable square wave .and after getting the square wave from this module ,i think it can make other module work well.but i find it not work;  the square wave inputting into the input pin is below 10M;

[Altera_Forum]

--- Quote Start ---  this module is only use to do with square wave,when the square wave with some unstable signal on its edge input into the input pin ,i want to use this module to get a stable square wave .and after getting the square wave from this module ,i think it can make other module work well.but i find it not work;  the square wave inputting into the input pin is below 10M;  --- Quote End ---    Hi,  there could be a lot of reasons why your design is not running on the FPGA. It would help when you at least post your <>.qsf in the forum, because then we can check your settings.  Kind regards  Gerd

[Altera_Forum]

--- Quote Start ---  Hi,   there could be a lot of reasons why your design is not running on the FPGA. It would help when you at least post your <>.qsf in the forum, because then we can check your settings.   Kind regards   Gerd  --- Quote End ---     Hi,I'm sorry! and I forget it . my <>.qsf is      # --------------------------------------------------------------------------# # # Copyright (C) 1991-2009 Altera Corporation# Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details.# # --------------------------------------------------------------------------# # # Quartus II# Version 9.0 Build 132 02/25/2009 SJ Full Version# Date created = 17:02:23 July 13, 2009# # --------------------------------------------------------------------------# # # Notes:# # 1) The default values for assignments are stored in the file:# zhengxing_assignment_defaults.qdf# If this file doesn't exist, see file:# assignment_defaults.qdf# # 2) Altera recommends that you do not modify this file. This# file is updated automatically by the Quartus II software# and any changes you make may be lost or overwritten.# # --------------------------------------------------------------------------#    set_global_assignment -name FAMILY "Cyclone II" set_global_assignment -name DEVICE EP2C5T144C8 set_global_assignment -name TOP_LEVEL_ENTITY zhengxing set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:02:23 JULY 13, 2009" set_global_assignment -name LAST_QUARTUS_VERSION 9.0 set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name VERILOG_FILE zh.v set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" set_global_assignment -name MISC_FILE "E:/cheng_xu/zhengxing/zhengxing.dpf" set_global_assignment -name QIP_FILE pll_0.qip set_global_assignment -name BDF_FILE zhengxing.bdf set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_location_assignment PIN_17 -to clk set_location_assignment PIN_51 -to data_in set_location_assignment PIN_48 -to data_out set_location_assignment PIN_75 -to rst set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL" set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS1 set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" set_global_assignment -name VECTOR_WAVEFORM_FILE zhengxing.vwf set_global_assignment -name SETUP_HOLD_DETECTION ON set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED ON set_global_assignment -name SIGNALTAP_FILE stp1.stp set_global_assignment -name ENABLE_SIGNALTAP OFF set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp       thank you!

[Altera_Forum]

--- Quote Start ---  Hi,I'm sorry! and I forget it . my <>.qsf is       # --------------------------------------------------------------------------#  #  # Copyright (C) 1991-2009 Altera Corporation # Your use of Altera Corporation's design tools, logic functions  # and other software and tools, and its AMPP partner logic  # functions, and any output files from any of the foregoing  # (including device programming or simulation files), and any  # associated documentation or information are expressly subject  # to the terms and conditions of the Altera Program License  # Subscription Agreement, Altera MegaCore Function License  # Agreement, or other applicable license agreement, including,  # without limitation, that your use is for the sole purpose of  # programming logic devices manufactured by Altera and sold by  # Altera or its authorized distributors. Please refer to the  # applicable agreement for further details. #  # --------------------------------------------------------------------------#  #  # Quartus II # Version 9.0 Build 132 02/25/2009 SJ Full Version # Date created = 17:02:23 July 13, 2009 #  # --------------------------------------------------------------------------#  #  # Notes: #  # 1) The default values for assignments are stored in the file: # zhengxing_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf #  # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. #  # --------------------------------------------------------------------------#    set_global_assignment -name FAMILY "Cyclone II" set_global_assignment -name DEVICE EP2C5T144C8 set_global_assignment -name TOP_LEVEL_ENTITY zhengxing set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:02:23 JULY 13, 2009" set_global_assignment -name LAST_QUARTUS_VERSION 9.0 set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name VERILOG_FILE zh.v set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" set_global_assignment -name MISC_FILE "E:/cheng_xu/zhengxing/zhengxing.dpf" set_global_assignment -name QIP_FILE pll_0.qip set_global_assignment -name BDF_FILE zhengxing.bdf set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_location_assignment PIN_17 -to clk set_location_assignment PIN_51 -to data_in set_location_assignment PIN_48 -to data_out set_location_assignment PIN_75 -to rst set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL" set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS1 set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" set_global_assignment -name VECTOR_WAVEFORM_FILE zhengxing.vwf set_global_assignment -name SETUP_HOLD_DETECTION ON set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED ON set_global_assignment -name SIGNALTAP_FILE stp1.stp set_global_assignment -name ENABLE_SIGNALTAP OFF set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp       thank you!  --- Quote End ---    Hi,  I did not see your verilog file ( in your first post) in the qsf. Are you using the zhengxing.bdf ? Is your reset signal connected ? Polarity ?  Kind regards  Gerd

[Altera_Forum]

--- Quote Start ---  Hi,   I did not see your verilog file ( in your first post) in the qsf. Are you using the zhengxing.bdf ? Is your reset signal connected ? Polarity ?   Kind regards   Gerd  --- Quote End ---     oh! i've changed the name of the module ,and its name is zh.v ,and use it in zhengxing.bdf

[Altera_Forum]

--- Quote Start ---  oh! i've changed the name of the module ,and its name is zh.v ,and use it in zhengxing.bdf  --- Quote End ---    Hi.  I assume you have your block conneted in the right way. Did you check your reset signal polarity ? What is your clock frequency and what is the toggling rate of your data_in?   Kind regards  Gerd

[Altera_Forum]

oh ! i changed the name of this module in my project in this afternoon, and it's name is zh.v,and use it in the zhengxing.bdf ,so it's no problem aboat this project! and i also use the signaltap to see the state machine, it doesn't work.but when i press the reset ,the register of counter and data_out is 

changed to '0',but when i don't press the reset ,the register of counter is changed from '0' to '3' all the time,and the state machine has no reaction.and the data_out is always high!

[Altera_Forum]

--- Quote Start ---  Hi.   I assume you have your block conneted in the right way. Did you check your reset signal polarity ? What is your clock frequency and what is the toggling rate of your data_in?    Kind regards   Gerd  --- Quote End ---     oh ! i changed the name of this module in my project in this afternoon, and its name is zh.v,and use it in the zhengxing.bdf ,so it's no problem aboat this project! and i also use the signaltap to see the state machine,but it doesn't work.when i press the reset ,the register of counter and data_out is be changed to '0',but when i don't press the reset ,the register of counter is changed from '0' to '3' all the time,and the state machine has no reaction.   the signal of clk_200M is from pll ,it's 200M,and data_in is the input of sqare wave ,and the rst is the input of reset, the out _data is the output of square wave afte this module ,and the square wave of data_in is under 10M,

[Altera_Forum]

--- Quote Start ---  oh ! i changed the name of this module in my project in this afternoon, and it's name is zh.v,and use it in the zhengxing.bdf ,so it's no problem aboat this project! and i also use the signaltap to see the state machine, it doesn't work.but when i press the reset ,the register of counter and data_out is  changed to '0',but when i don't press the reset ,the register of counter is changed from '0' to '3' all the time,and the state machine has no reaction.and the data_out is always high!  --- Quote End ---    Hi,  did you capture the data_in with signaltap ? Which clock did you use for signaltap ?  Kind regards  Gerd

[Altera_Forum]

--- Quote Start ---  Hi,   did you capture the data_in with signaltap ? Which clock did you use for signaltap ?   Kind regards   Gerd  --- Quote End ---     i use 200M in the signal tap,so it should be captured !

[Altera_Forum]

--- Quote Start ---  the signal of clk_200M is from pll ,it's 200M,and data_in is the input of sqare wave ,and the rst is the input of reset, the out _data is the output of square wave afte this module ,and the square wave of data_in is under 10M,  --- Quote End ---     200 MHz, generated from your PLL, is a rather fast clock for a Cyclone-II.    1) Make sure with the TimeQuest Timing Analyzer that your design meets the timing requirements. (200 MHz means a 5nsec clock period).   2) You could first try to feed your design with a slower clock and debug it. You could take your external clock signal for that. That is probably much lower than the 200 MHz.

[Altera_Forum]

--- Quote Start ---  200 MHz, generated from your PLL, is a rather fast clock for a Cyclone-II.    1) Make sure with the TimeQuest Timing Analyzer that your design meets the timing requirements. (200 MHz means a 5nsec clock period).   2) You could first try to feed your design with a slower clock and debug it. You could take your external clock signal for that. That is probably much lower than the 200 MHz.  --- Quote End ---     i also try it with 20M,it doesn't work ! this is the a picture of timing analyzer!

[Altera_Forum]

Your code should work, and the data_out should react on the change of data_in. There are a number of possible causes that you should make sure to work: 

 1) Check that the polarity of the rst signal is OK as pletz suggests. (You seem to have done this). 2) Make sure that your clock speed is not too high. 200MHz is high for a Cyclone-II. It depends on the specific configuration of your circuit if this will work or not... 3) Make sure that the output can change as pletz suggested. (You seem to have checked this too). 4) You should check that your data_in signal is OK. You could test your design by having data_in connected to a switch, the state to two LEDs and the data_out to a LED. You should be able to see the states of the wait_high and wait_low when you push on the data_in button. Your data_out LED should follow your data_in button.   Hope this helps

[Altera_Forum]

have had simular problems, problem is don't remember how i got around them all. some just went away when i changed something. :rolleyes:  

 one i remember: check rtl veiwer and see if it is correct. have found corrupted rtl. got around this by clicking on a block and updataing 'all' blocks.  another problem went away when i installed singnal tap to watch it. you have indicated that you have signal tap installed. what does it say?  what does the floor plan show for that pin?