division procedure in schematic programming

[Altera_Forum]

i want divide an analog input say 4sinwt....so max value is 4. i want to divide the signal by 5 so output will be 0.8sinwt. so how i program through lpm_divide blockto get such result.

[Altera_Forum]

lets start with this fact: no inputs on FPGA are analogue. They are all digital. 

Secondly, the schematic is NOT programming.  Finally, if you want to divide your input by 5, just set the second input to be 5.

[Altera_Forum]

no i am talking about that suppose i giving the input pin of adc is an analog signal say 4sinwt. and i want to divide it by 5 to get 0.8sinwt. i represent the input 4sinwt as va[15..0] which is a 16 bit no. this value i taken as the input of lpm_divide block as numerator. so how bit wide i select the denominator for represent 5 what will be the value of denominator [ its decimal value 5 or pu value and bit length plz explain ] 

 after division operation to display the result on CRO through dac from which 12 bit i taken from quotient of lpm_divide block for input of the DAC(i have taken 2 input DAC).

[Altera_Forum]

the denominator needs to be at least 3 bits. The number of bits is determined by the number of bits you require for the fraction component.  

How many bits are fractional on the input? given that it is 4sinwt, I assume you have at least 4 integer and 12 fractional?

[Altera_Forum]

so i select the denominator is 5 and consider as 3 bit input for denominator. and input of my numerator is 16 bit.if i take the integer part as 4 bit and fraction part as 12 bit . actually i just started to work with fpga recently. so after division operation to display the result on CRO through dac from which 12 bit i taken from quotient of lpm_divide block for input of the DAC(i have taken 2 input DAC). so if explain it with an explain then it really very clear to understand for me.