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error in pin planner

Altera_Forum
Honored Contributor II
‎12-29-2014 04:19 AM
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hello all, 

 

i got one error in pin planner that is Error (176172): Can't place node "hsync_n" -- node is a differential I/O node. 

 

with this post i am attached .Qsf file. i dont know why this error comes and how to resolve it. 

i also check 'IO_MAXIMUM_TOGGLE_RATE "0MHz"' settings that was not removed. so plz give me some solution about this error.
ALTERA_VHDL.zip
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Altera_Forum
Honored Contributor II
‎01-05-2015 03:26 PM
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http://www.alteraforum.com/forum/showthread.php?t=46925 (http://www.alteraforum.com/forum/showthread.php?t=46925) 

As per my response to your other thread open with the same question... 

 

A quick look at the .qsf you posted shows a conflict between the 'hsync_p' & 'hsync_n' signals. One is 1.8V, the other 2.5V. 

 

I think you should be generating hsync as a differential signal. However, your qsf shows different single ended I/O standards for each half of the pair. 

 

If you still need help let me know. 

 

Happy New Year, 

Alex
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