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how I can create a custom instruction to manage operations on vectors

Altera_Forum
Honored Contributor II
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hi,  

I'm trying to write a VHDL component that makes a multiplication between two matrices or vectors. the component will be a custom instruction that I would use in nios in the following way  

 

 

float vett1 [10], vett2 [10],  

float result [] = alt_mult (vett1, vett2); 

 

the questions are as follows  

 

 

how can I send arrays to the function mult vhdl?  

where I have to save them? 

 

 

can anyone help me?  

if there is a similar project you can send me the code?
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Altera_Forum
Honored Contributor II
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A custom instruction has a maximum of two 32bit inputs and one 32bit output. 

Search these lists for similar requests - and those for 128bit (and larger) maths.
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Altera_Forum
Honored Contributor II
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Here is one such thread: 

http://www.alteraforum.com/forum/showthread.php?t=40312 

 

With large data, many people decide to not use custom instruction, and instead opt for Avalon-MM Slave accelerator, fed by DMA controller.
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Altera_Forum
Honored Contributor II
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thanks for your answers,  

I was thinking of saving the data in the onchip memory, but do not know how ...  

how do I read / write from onchip memory from nios?  

how to read / write from a component in VHDL?
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Altera_Forum
Honored Contributor II
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Easily :-) 

Also (IIRC) qsys will directly expose the 2nd port of a memory block - so you can directly attach external VHDL to it. 

Or you write your own Avalon slave interface for the memory block inside your VHDL. 

In the latter case you may not be able to use the more efficient 'tightly coupled data' interface for the memory block (although that would also proclude DMA access to it).
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Altera_Forum
Honored Contributor II
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hi,  

I used Avalon MM Slave template, I put the file in QSYS slave_template.v and I connected it to NIOS  

This template offers 16 registers 

I can read write data from register with the operations of IORD_32DIRECT (), IOWR_32Direct ().  

Now the problem is how do I create a component verilog / vhdl who make some operations with the values ​​loaded into the registers?  

in the file .v I've seen that the following signals are available:  

user_dataout_X  

user_datain_X  

how can I use them? 

 

can you give me a link to some examples?
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