output to header on DE0-nano cyclone IV E

[Altera_Forum]

DE0-nano FPGA identifies header output as example GPIO_2 header JP1 as Pin 5. 

I have used the DE0-nano FPGA system generator to set the project. I used the .bdf file system to create the code. How do I get the signal to an output pin. I get a ripple type signal.  The difference between the max and Min is only 150 MV where the Max is 3.3 and the Min is 3.15    

[Altera_Forum]

I think I ask the wrong question. 

The DE0-Nano board user manual shows Header JP1 PIN 5 is GPIO_02. How is this equated to chip pin in the pin planner.

[Altera_Forum]

If you have a look at the board schematics you should see which FPGA pin the CPIO_02 signal is connected to.

[Altera_Forum]

Thanks. 

The pin assignments are also in the user manual. Some time in the past I had used the back annotation and it was wrong. Don't use the back annotator. Had to remove all assignments and reassign.  Wrong you must use the back annotation.